Xxicn - Maskable Interrupt Control Registers - NEC V850ES/F 3-L Series User Manual

Interrupt Controller (INTC)

5.3.4 xxICn - Maskable interrupt control registers

Access
Address
Initial Value
Bit position Bit name
7 xxIFn
6 xxMKn
xxPR2 to
2 to 0
xxPR0
Note
Note
An interrupt control register is assigned to each interrupt request (maskable
interrupt) and sets the control conditions for each maskable interrupt request.
This register can be read/written in 1-bit or 8-bit units.
FFFF F110 to FFFF F194
H
47 . The register is initialized by any reset
H
7
xxICn xxIFn xxMKn
This is an interrupt request flag.
0: Interrupt request not issued
1: Interrupt request issued
The flag xxIFn is reset automatically by the hardware if an interrupt request is
acknowledged.
This is an interrupt mask flag.
0: Enables interrupt processing
1: Disables interrupt processing (pending)
8 levels of priority order are specified for each interrupt.
xxPR2 xxPR1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
xx: identification name of each peripheral unit (LVIL, LVIH, P, TAA0OV-TAA4OV,
TAA0CC-TAA4CC, TM0EQ, CB0R-CB1R, CB0T-CB1T, UD0S-UD2S, UD0R-
UD2R, UD0T-UD2T, IIC0, AD, C0ERR, C0WUP, C0REC, C0TRX, KR, WTI,
WT, FL)
The address and the availability of each interrupt control register for each
device is shown in the following table.
The symbols used in the table mean:
√ : register available for the device
–: register not available for the device
User's Manual U18743EE1V2UM00
H
6 5 4
0 0
Function
xxPR0 Interrupt priority specification bit
0 Specifies level 0 (highest)
1 Specifies level 1
0 Specifies level 2
1 Specifies level 3
0 Specifies level 4
1 Specifies level 5
0 Specifies level 6
1 Specifies level 7 (lowest)
Chapter 5
3 2 1
0 xxPR2 xxPR1
0
xxPR0
237