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Chapter 4
Note
4.2.5 Clock Monitor control registers
(1)
Access
Address
Initial Value
Table 4-17
Bit position
Bit name
0
CLME
Note
184
1.
Do not rewrite the PRSCM0 register during Watch Timer operation.
2.
Set the PRSM0 and PRSCM0 registers according to the main clock
frequency that is used to obtain an f
For details and a calculation example, please refer to "Operation of Prescaler3"
on page 216.
These registers control and reflect the operation of the Clock Monitor.
CLM - Main oscillator Clock Monitor mode register
The 8-bit CLM register is used to enable the monitor for the main oscillator
clock.
This register can be read/written in 8-bit or 1-bit units.
Writing to this register is protected by a special sequence of instructions.
Please refer to "CPU System Functions" on page 135 for details.
FFFF F870
.
H
00
. This register is cleared by any reset.
H
7
6
5
0
0
0
R
R
R
CLM register contents
Clock Monitor enable:
for
0: Clock Monitor
1: Clock Monitor for main oscillator enabled.
This bit can only be cleared by reset.
1.
CLM.CLME can be set at any time. However, the Clock Monitor is only
activated after the main oscillator has stabilized, indicated by OSTC.MSTS
= 1.
2.
When reset is generated by the clock monitor, CLM.CLME is cleared to 0
and RESF.CLMRF is set to 1.
User's Manual U18743EE1V2UM00
frequency of 32,768 KHz.
BRG
4
3
2
0
0
0
R
R
R
Function
main oscillator disabled.
Clock Generator
1
0
0
CLME
R
R/W
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