Chapter 17
17.7 I
17.7.1 Master device operation
(1)
488
2
C Interrupt Request Signals (INTIICn)
The following shows the value of the IICSn register at the INTIICn interrupt
request signal generation timing and at the INTIICn signal timing.
Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception)
<1> When WTIMn bit = 0
ST
AD6 to AD0
♦
1: IICSn register = 1000X110B
♦
2: IICSn register = 1000X000B
♦
3: IICSn register = 1000X000B (WTIMn bit = 1)
♦
4: IICSn register = 1000XX00B
∆ 5: IICSn register = 00000001B
♦
Remarks 1.
∆: Generated only when SPIEn bit = 1
X: don't care
<2> When WTIMn bit = 1
ST
AD6 to AD0
♦
1: IICSn register = 1000X110B
♦
2: IICSn register = 1000X100B
♦
3: IICSn register = 1000XX00B
∆ 4: IICSn register = 00000001B
♦
Remarks 1.
∆: Generated only when SPIEn bit = 1
X: don't care
User's Manual U18743EE1V2UM00
R/W
ACK
D7 to D0
♦
1
: Always generated
R/W
ACK
D7 to D0
♦
1
: Always generated
2
I
C Bus (IIC)
SPTn bit = 1
ACK
D7 to D0
ACK
♦
♦
2
3
SPTn bit = 1
ACK
D7 to D0
ACK
♦
2
↓
SP
♦
∆5
4
↓
SP
♦
∆4
3