NEC V850ES/F 3-L Series User Manual page 459

2
I C Bus (IIC)
Master CPU1
Slave CPU1
Address 1
Figure 17-2
Table 17-1
A serial bus configuration example is shown below.
Serial data bus
SDA
Serial clock
SCL
Serial bus configuration example using I
2
I Cn includes the following hardware.
2
Configuration of I Cn
Item
Registers
Control registers
User's Manual U18743EE1V2UM00
+V +V
DD DD
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
2
C bus
Configuration
IIC shift register n (IICn)
Slave address register n (SVAn)
IIC control register n (IICCn)
IIC status register n (IICSn)
IIC flag register n (IICF0n)
IIC clock select register n (IICCLn)
IIC function expansion register n (IICXn)
IIC division clock select registers (OCKSn)
Chapter 17
Master CPU2
Slave CPU2
Address 2
Slave CPU3
Address 3
Slave IC
Address 4
Slave IC
Address N
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