NEC V850ES/F 3-L Series User Manual page 234

Chapter 5
Main routine
EI
Interrupt request a
(level 3)
Interrupt request c
Interrupt request d
(level 3)
Interrupt request e
Interrupt request f
(level 2)
Interrupt request g
(level 1)
Figure 5-7
Caution
234
Processing of a
EI
Interrupt
request b
(level 2)
Processing of c
(level 2)
Processing of d
Processing of e
EI
(level 3)
Processing of f
Processing of g
EI
Interrupt request h
(level 1)
Processing of h
Example of processing in which another interrupt request is issued
while an interrupt is being processed (1/2)
The values of the EIPC and EIPSW registers must be saved before executing
multiple interrupts. When returning from multiple interrupt servicing, restore the
values of EIPC and EIPSW after executing the DI instruction.
User's Manual U18743EE1V2UM00
Interrupt Controller (INTC)
Processing of b
Interrupt request b is acknowledged because the
priority of b is higher than that of a and interrupts are
enabled.
Although the priority of interrupt request d is higher
than that of c, d is held pending because interrupts
are disabled.
Interrupt request f is held pending even if interrupts are
enabled because its priority is lower than that of e.
Interrupt request h is held pending even if interrupts are
enabled because its priority is the same as that of g.