NEC V850ES/F 3-L Series User Manual page 303

Bus Control Unit (BCU)
Table 9-6
Bit position Bit name
2 to 0 VSWL[2:0]
Table 9-7
Note
VSWC register contents (2/2)
Data wait for internal bus:
VSWL2 VSWL1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
The following setups are recommended for VSWC:
Recommended timing for internal bus
System clock (f )
CPU
SUWL
VSWL
VSWC
1. The bits marked with 0 must always be 0.
2. This register must be initialized after RESET.
Preliminary User's Manual U18743EE1V2UM00
Function
VSWL0 Number of data wait states
0
1 1 CPU system clock (VBCLK)
0 2 CPU system clock (VBCLK)
1 3 CPU system clock (VBCLK)
0 4 CPU system clock (VBCLK)
1 5 CPU system clock (VBCLK)
0 6 CPU system clock (VBCLK)
1 7 CPU system clock (VBCLK)
≤16 MHz ≤20 MHz
0 0
0 1
00 01
H H
Chapter 9
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