NEC V850ES/F 3-L Series User Manual page 223

32-bit single-chip microcontroller

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Interrupt Controller (INTC)

not available for V850ES/FE3-L, V850ES/FF3-L

Interrupt/Exception Source

Generating Source

CSIB1 reception completion /

reception error

CSIB1 consecutive transmission

write enable

UARTD0 status interrupt

UARTD0 reception completion

UARTD0 consecutive transmission

UARTD1 status interrupt

UARTD1 reception completion

UARTD1 consecutive transmission

IIC0 transfer completion

A/D conversion completion

CAN0 wake–up

CAN0 reception

CAN0 transmission

Key return interrupt

Watch Timer interval

Watch Timer reference time

Flash programming completion

External interrupt 8

External interrupt 9

External interrupt 10

UARTD2 status interrupt

UARTD2 reception completion

UARTD2 consecutive transmission

Restored PC:

The execution address of the illegal instruction when an illegal opcode

exception occurs is calculated by (Restored PC – 4).

User's Manual U18743EE1V2UM00

interrupt requests are generated at the same time.

The highest priority is 0.

The value of the PC saved to EIPC or FEPC when

interrupt/exception processing is started. However, the

value of the PC saved when an interrupt is

acknowledged during division (DIV, DIVH, DIVU,

DIVHU) instruction execution is the value of the PC of

the current instruction (DIV, DIVH, DIVU, DIVHU).

The PC value that starts the processing following

interrupt/exception processing.

NEC V850ES/F 3-L Series User Manual page 223

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