Configuration - NEC V850ES/F 3-L Series User Manual

Chapter 17

17.3 Configuration

Figure 17-1
SDAn
Noise
eliminator
N-ch open-drain
output
SCLn
Noise
eliminator
N-ch open-drain
output
f
Prescaler
XP1
OCKSENn OCKSTHn OCKSn1
IIC division clock select
register m (OCKSn)
458
The block diagram of the I
2
Block diagram of I
IIC control register n
(IICCn)
IICEn LRELn WRELnSPIEn WTIMn ACKEn STTn SPTn
Set
Slave address
Clear
register n (SVAn)
Match signal
SO latch
IIC shift
DQ
register n (IICn)
Data hold
time correction
circuit
Acknowledge detector
Star t condition
detector
Stop condition
detector
Serial clock counter
Serial clock
controller
Prescaler
IICLKPS = f to f /5
XP1 XP1
OCKSn0 CLDn DADn SMCn DFCn CLn1 CLn0
User's Manual U18743EE1V2UM00
2
Cn is shown below.
Cn
Internal bus
IIC status register n (IICSn)
MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
Start condition
generator
CLn1,
CLn0
Acknowledge
output circuit
Interrupt request
signal generator
Serial clock
wait controller
IICLKTC
CLXn
IIC clock select IIC function expansion
register n (IICCLn) register n (IICXn)
Internal bus
2
I C Bus (IIC)
Wake-up controller
INTIICn
STCFn IICBSYn STCENn IICRSVn
IIC flag register n
(IICFn)
Bus status
detector