Address Match Detection Method; Error Detection - NEC V850ES/F 3-L Series User Manual

32-bit single-chip microcontroller

Table of Contents

17.9 Address Match Detection Method

Wait cancellation method

The four wait cancellation methods are as follows.

By setting the IICCn.WRELn bit to 1

By writing to the IICn register

By start condition setting (IICCn.STTn bit = 1)

By stop condition setting (IICCn.SPTn bit = 1)

When an 8-clock wait has been selected (WTIMn bit = 0), the output level of

the ACK signal must be determined prior to wait cancellation.

Stop condition detection

The INTIICn signal is generated when a stop condition is detected.

C bus mode, the master device can select a particular slave device by

transmitting the corresponding slave address.

Address match detection is performed automatically by hardware. The INTIICn

signal occurs when a local address has been set to the SVAn register and

when the address set to the SVAn register matches the slave address sent by

the master device, or when an extension code has been received.

C bus mode, the status of the serial data bus pin (SDA0n) during data

transmission is captured by the IICn register of the transmitting device, so the

data of the IICn register prior to transmission can be compared with the

transmitted IICn data to enable detection of transmission errors. A

transmission error is judged as having occurred when the compared data

values do not match.

User's Manual U18743EE1V2UM00