NEC V850ES/F 3-L Series User Manual page 558

32-bit single-chip microcontroller
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Chapter 18
Table 18-22
Address
Symbol
a
offset
52
CnLEC (W)
H
52
CnLEC (R)
H
53
CnINFO
H
54
CnERC
H
55
H
56
CnIE (W)
H
57
H
56
CnIE (R)
H
57
H
58
CnINTS (W)
H
59
H
58
CnINTS (R)
H
59
H
5A
CnBRP
H
5C
CnBTR
H
5D
H
5E
CnLIPT
H
60
CnRGPT (W)
H
61
H
60
CnRGPT (R)
H
61
H
F62
CnLOPT
H
64
CnTGPT (W)
H
65
H
64
CnTGPT (R)
H
65
H
66
CnTS (W)
H
67
H
66
CnTS (R)
H
67
H
68
to FF
-
H
H
a)
Base address: <CnRBaseAddr>
558
CAN module register bit configuration (2/2)
Bit 7/15 Bit 6/14 Bit 5/13
0
0
0
0
0
0
REPS
0
0
Clear
CIE5
0
0
Set CIE5
0
0
CIE5
0
0
0
0
Clear
CINTS5
0
0
0
0
CINTS5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
User's Manual U18743EE1V2UM00
Bit 4/12
Bit 3/11
0
0
0
0
0
0
0
BOFF
TECS1
TEC7 to TEC0
REC6 to REC0
Clear
Clear
CIE4
CIE3
Set CIE4
Set CIE3
CIE4
CIE3
0
0
0
Clear
Clear
CINTS4
CINTS3
0
0
0
CINTS4
CINTS3
0
0
0
TQPRS7 to TQPRS0
0
0
SJW1, SJW0
0
LIPT7 to LIPT0
0
0
0
0
0
0
0
0
0
RGPT7 to RGPT0
LOPT7 to LOPT0
0
0
0
0
0
0
0
0
0
TGPT7 to TGPT0
0
0
0
0
0
0
0
0
0
0
0
0
Access prohibited (reser ved for future use)
CAN Controller (CAN)
Bit 2/10
Bit 1/9
Bit 0/8
0
0
LEC2
LEC1
LEC0
TECS0
RECS1
RECS0
Clear
Clear
Clear
CIE2
CIE1
Set CIE2
Set CIE1
Set CIE0
CIE2
CIE1
0
0
Clear
Clear
Clear
CINTS2
CINTS1
CINTS0
0
0
CINTS2
CINTS1
CINTS0
0
0
TSEG13 to TSEG10
TSEG22 to TSEG20
0
0
Clear
ROVF
0
0
0
RHPM
ROVF
0
0
Clear
TOVF
0
0
0
THPM
TOVF
Clear
Clear
Clear
TSLOCK
TSSEL
TSEN
Set
Set
TSLOCK
TSSEL
TSEN
TSLOCK
TSSEL
TSEN
0
0
0
CIE0
CIE0
0
0
0
0
0
Set
0

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