NEC V850ES/F 3-L Series User Manual page 162

Chapter 4
(2)
Peripheral base
clock f
XP1
Prescaler1
(3)
Clock for UARTDn,
TAAn, MLM
Clock for TMM0
Clock for CANn
Clock for WT
PCL
CLKOUT
162
The clock sources MainOSC, PLL and 8 MHz internal oscillator can generate
the master clock f . This clock forms the input to Prescaler2. Prescaler2 can
XX
divide the master clock f
PCC register.
Prescaler2, the SubOSC, or the 240 KHz internal oscillator can generate the
CPU core clock (f ) and the CPU system clock (f
CPU
between f and f
VBCLK CPU
f is the clock supplied to the INTC, ROM, and RAM blocks. It is directly
VBCLK
available at the CLKOUT pin.
Peripheral clocks
The middle and right-hand side of Figure 4-1 on page 160 shows how the
clocks for the peripheral modules are generated and distributed.
f is the clock source for the peripheral base clock f
XX
General purpose peripheral clocks are provided by fixed Prescaler1.
This prescaler generates the peripheral clocks (f
supplied to on-chip peripheral functions such as timers, serial interfaces and A/
D Converter.
Special clocks
The Clock Generator provides special clocks for certain peripherals.
This clock can be derived from f
frequency which is either f
the option bytes.
Note that f stops in all IDLE modes while f
XP1
The timers TAA1 and TAA3 can also be supplied with the SubOSC clock f
Clock source for timer TMM can be any of the oscillators. The selection
between f or f is made by bit SELCNT0.ISEL07.
XP1 RH
The CAN interfaces can be clocked by f
SELCNTx register. Select f
clock oscillator to the CAN controller.
After reset, the Watch Timer is clocked by the SubOSC (f
changed when the main oscillator has stabilized. WT can then be clocked by
the output of Prescaler3 that supplies also the CSIB0 block.
Prescaler3 serves as a baud rate generator. It is controlled by the registers
PRSM0 and PRSCM0. For details see also "Operation of Prescaler3" on
page 216.
The Clock Generator has a programmable clock (PCL) output.This output can
deliver a fraction of f
PLSS
from f . It is controlled by register PCLM and must be enabled by setting
PLLO
PCLM.PCLE.
This output provides the CPU system clock f
stability period, its state becomes Hi-Z.
User's Manual U18743EE1V2UM00
by 1, 2, 4, 8, 16 or 32. Its operation is set in the
XX
is that the latter can be stopped in HALT mode.
or f . Both f
XP1 XP2
or f /2, depending on the setting of bit PRSI in
XX XX
XP2
or by f
XP1
when directly supplying the clock generated by a
XC
(f divided by 4, 8, 16, or 32), which is derived
PLSS
VBCLK
Clock Generator
). The only difference
VBCLK
.
XP1
to f /1024) to be
XP1 XP1
and f have the same
XP1 XP2
stops only in IDLE2 mode.
, as chosen by a bit in the
XC
). This can be
XT
. During the oscillation
.
XT