Page 1 Preliminary User’s Manual V850E/CA1 ATOMIC 32-/16-bit Single-Chip Microcontroller Hardware µPD703123, µPD70F3123 Document No. U14913EE1V0UM00 Date Published October 2001  NEC Corporation 2001 Printed in Germany...
Page 2 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 3 The information in this document is current as of 20.09.2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC’s data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country.
Page 4 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability •...
Page 5 Preface Readers This manual is intended for users who want to understand the functions of the V850E/CA1 (nickname Atomic) (µPD70F3123, µPD703123). Purpose This manual presents the hardware manual of V850E/CA1. Organization This system specification describes the following sections: • Pin function •...
Page 6 [MEMO] Preliminary User’s Manual U14913EE1V0UM00...
Page 7: Table Of Contents
Table of Contents Chapter 1 Introduction ..........21 General .
Page 8 Idle State Insertion Function ..........141 Bus Priority Order .
Page 9 Maskable Interrupts ........... 195 7.3.1 Operation .
Page 10 Timer E ............. 256 9.2.1 Features (timer E) .
Page 11 13.4 Operating Condsiderations ..........446 13.4.1 Rules to be observed for correct baud rate settings .
Page 12 16.8 Port CT ............. 557 16.9 Port CM .
Page 13 List of Figures Figure 1-1: Pin configuration of the µPD70(F)3123 microcontroller ..........24 Figure 1-2: Block diagram of the µPD70(F)3123 microcontroller ..........26 Figure 2-1: Pin I/O Circuits ......................51 Figure 3-1: CPU Register Set ....................... 54 Figure 3-2: Program Counter (PC) ....................55 Figure 3-3: Interrupt Source Register (ECR) ................
Page 14 Figure 7-12: Interrupt Mask Registers 0 to 3 (IMR0 to IMR3) ............205 Figure 7-13: In-Service Priority Register (ISPR) ................206 Figure 7-14: Maskable Interrupt Status Flag (ID) ................. 206 Figure 7-15: Timer E Input Circuit Overview ................. 207 Figure 7-16: Port Interrupt Input Circuit Overview ................
Page 15 Figure 9-28: External Control Timing of Timer E ................283 Figure 9-29: Operation in Timer E Up/Down Count Mode ............284 Figure 9-30: Timer E Timing in 32-Bit Cascade Operation Mode ..........285 Figure 9-31: Block Diagram of Timer E Multiplex Count Generation Circuit ......... 286 Figure 9-32: Timer E Multiplex Count Timing ................
Page 16 Figure 12-32: Serial I/O Shift Registers 0, 1 (SIO0, SIO1) ............. 351 Figure 12-33: Serial I/O Shift Registers L0, L1 (SIOL0, SIOL1) ............. 352 Figure 12-34: Timing Chart in Single Transfer Mode (1/2) ............. 353 Figure 12-35: Timing Chart According to Clock Phase Selection (1/2) ........... 355 Figure 12-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2) .....
Page 17 Figure 13-43: CAN 1 to 3 Bus Diagnostic Information Registers (C1DINF to C3DINF) ....445 Figure 13-44: Sequential CAN Data Read by CPU ................ 449 Figure 13-45: State Transition Diagram for CAN Modules ............. 451 Figure 13-46: General Initialisation Sequence for the CAN Interface ..........452 Figure 13-47: Initialisation Sequence for a CAN module ..............
Page 18 Figure 16-18: Port 4 (P4) ........................ 544 Figure 16-19: Port 4 Mode Register (PM4) ..................544 Figure 16-20: Port 4 Mode Control Register (PMC4) ..............545 Figure 16-21: Port 5 (P5) ........................ 546 Figure 16-22: Port 5 Mode Register (PM5) ..................546 Figure 16-23: Port 5 Mode Control Register (PMC5) ..............
Page 19 List of Tables Table 3-1: Program Registers ......................55 Table 3-2: System Register Numbers ..................... 56 Table 3-3: Register Initial Values by Operation Modes ..............58 Table 3-4: List of Peripheral I/O Registers (Sheet 1 of 10) ............71 Table 3-5: List of programmable peripheral I/O registers (Sheet 1 of 32) ........
Page 20 Table 13-18: Format of 64-bit Temporary Buffer ................464 Table 13-19: Format of Temporary Sum ..................464 Table 14-1: Correspondence between ADCRm (m = 0 to 11) Register Names and Addresses ..497 Table 14-2: Correspondence between each Analog Input Pin and ADCRm Registers ....498 Table 15-1: Maximum Number of Display Pixels ................
Page 21: Chapter 1 Introduction
Chapter 1 Introduction 1.1 General The V850E/CA1 / ATOMIC single chip microcontroller, is a member of NEC's V850 32-bit RISC family, which match the performance gains attainable with RISC-based controllers to the needs of embedded control applications. The V850 CPU offers easy pipeline handling and programming, resulting in com- pact code size comparable to 16-bit CISC CPUs.
Page 22: Device Features
Chapter 1 Introduction 1.2 Device Features • - Core: V850E - Number of instructions: - Min. instruction execution time: 50 ns (@ f = 20 MHz) - General registers: 32 bits x 32 • Instruction set: - V850E (compatible with V850 plus additional powerful instructions for reducing code and increas- ing execution speed) - Signed multiplication (16 bits x 16 bits →...
Page 23: Application Fields
Chapter 1 Introduction • Full-CAN Interface: - Full CAN 3 channel • CAN Bridge for Gateway applications • Timers - 16/32-bit multi purpose timer/event counter: 3 channel - 16-bit OS timer 2 channel - Watch timer: 1 channel - Watchdog timer: 1 channel •...
Page 24: Pin Configuration (Top View)
Chapter 1 Introduction 1.5 Pin Configuration (Top View) Figure 1-1: Pin configuration of the µPD70(F)3123 microcontroller P30/TIE0/INTPE00 P14/CRXD3 P31/TOE10/INTPE10 P13/CTXD2 P12/CRXD2 P32/TOE20/INTPE20 P11/CTXD1 P33/TOE30/INTPE30 P34/TOE40/INTPE40 P10/CRXD1 P35/TCLRE0/INTPE50 P25/SCK1 P40/TIE1/INTPE01 P24/SO1 P41/TOE11/INTPE11 P23/SI1 P42/TOE21/INTPE21 SS 54 P43/TOE31/INTPE31 DD 54 P44/TOE41/INTPE41 PP 1 P45/TCLRE1/INTPE51 P22/SCK0 P50/TIE2/INTPE02...
Page 25 Chapter 1 Introduction Pin Identification A0 to A23 : Address Bus P60 to P65 : Port 6 D0 to D15 : Data Bus PAL0 to PAL15 Port AL ANI00 to ANI11 : Analog Input PAH0 to PAH7 : Port AH : Analog Power Supply PCM0, PCM1 : Port CM...
Page 26: Configuration Of Function Block
Chapter 1 Introduction 1.6 Configuration of Function Block 1.6.1 Block Diagram of µPD70(F)3123 Figure 1-2: Block diagram of the µPD70(F)3123 microcontroller power supply CPU Core Interrupt External Controller Interrupts A0 - A23 Barrel Hardware INTPE00-INTPE52 Shifter Multiplier D0 - D15 TIE0-TIE2 16-/32-bit Flash/...
Page 27: On-Chip Units
Chapter 1 Introduction 1.6.2 On-chip units The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits → 32 bits or 32 bits x 32 bits →...
Page 28 Chapter 1 Introduction Serial interface (SIO) A 3-channel asynchronous serial interface (UART), 2-channel clocked serial interface (CSI), and 3- channel FCAN are provided as serial interface. UART transfers data by using the TXDn and RXDn pins. (n = 0 - 2) CSI transfers data by using the SOn, SIn, and SCKn pins.
Page 29: Chapter 2 Pin Functions
Chapter 2 Pin Functions 2.1 List of Pin Functions The names and functions of this product’s pins are listed below. These pins can be divided into port pins and non-port pins according to their functions. Port pins Port Function Alternate Port 1 CRXD1 8-bit input/output port...
Page 30 Chapter 2 Pin Functions Port Function Alternate Port 6 CCLK/SEG34 6-bit input/output port INT0/SEG35 INT1/SEG36 INT2/SEG37 RXD2/SEG38 TXD2/SEG39 PAL0-PAL15 Port AL A0-A15 / 16-bit input/output port SEG23-SEG8 PAH0-PAH7 Port AH A16-A23 / 8-bit input/output port SEG7-SEG0 PDL0- Port DL D0-D15 PDL15 16-bit input/output port PCS2-PCS4...
Page 31 Chapter 2 Pin Functions Non-port pins Pin Name Function Alternate – Power supply 5 V DD50 DD54 – GND potential SS50 SS54 Note 1 – Connection for external capacities DD30 DD33 – GND potential SS30 SS33 Note 2 – Connection for external capacities to stabilize clock oscillator power supply input System clock oscillator connection pins.
Page 32 Chapter 2 Pin Functions Pin Name Function Alternate A0-A7 output address bus of external bus PAL0-PAL7/SEG23-SEG16 A8-A15 PAL8-PAL15/SEG15-SEG8 A16-A23 PAH0-PAH7/SEG7-SEG0 write strobe lower byte (bit 0-7) PCT0/SEG27 write strobe upper byte (bit 8-15) PCT1/SEG28 read strobe for external bus PCT4/SEG31 WAIT input control signal input for external bus...
Page 33 Chapter 2 Pin Functions Pin related to µPD70(F)3123 status Operating Status RESET STOP WATCH IDLE HALT idle state (TI) D0 to D15 N.A. operate operate Hi-Z/-- Hi-Z/-- Hi-Z/-- A0 to A23 N.A. Hi-Z Hi-Z Hi-Z operate operate CS2 to CS4 N.A.
Page 34: Description Of Pin Functions
Chapter 2 Pin Functions 2.2 Description of Pin Functions P10 to P17 (Port 1) … Input/output Port 1 is an 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P10 to P17 operate as serial interface (UART1, FCAN) input/output.
Page 35 Chapter 2 Pin Functions P20 to P27 (Port 2) … Input/output Port 2 is an 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P20 to P27 operate as serial interface (CSI0, CSI1, UART0) input/output.
Page 36 Chapter 2 Pin Functions P30 to P35 (Port 3) … Input/output Port 3 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P30 to P35 operate as RPU input/out- put and external interrupt request input.
Page 37 Chapter 2 Pin Functions P40 to P45 (Port 4) … Input/output Port 4 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P40 to P45 operate as RPU input/out- put and external interrupt request input.
Page 38 Chapter 2 Pin Functions P50 to P55 (Port 5) … Input/output Port 5 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode, P50 to P55 operate as RPU input/out- put and external interrupt request input.
Page 39 Chapter 2 Pin Functions P60 to P65 (Port 6) … Input Port 6 is an input/output port. Besides functioning as an input port, in control mode, P60 to P65 operate as segment signal output of LCD controller/driver, external CAN clock supply, serial interface (UART2) input/output and exter- nal interrupt request input.
Page 40 Chapter 2 Pin Functions PAL0 to PAL15 (Port AL) … Input/output Port AL is an 16-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these operate as the address bus (A0 to A15) when memory is expanded externally and segment signal output of LCD controller/driver.
Page 41 Chapter 2 Pin Functions PAH0 to PAH7 (Port AH) … Input/output Port AH is an 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these operate as the address bus (A16 to A23) for when memory is expanded externally and segment signal output of LCD controller/driver.
Page 42 Chapter 2 Pin Functions PDL0 to PDL15 (Port DL) … Input/output Port DL is a 16-/8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these operate as the data bus (D0 to D15) for when memory is expanded externally.
Page 43 Chapter 2 Pin Functions (10) PCS2 to PCS4 (Port CS) … Input/output Port CS is a 3-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), it operates as control sig- nal output when memory is expanded externally and segment signal output of LCD controller/driver.
Page 44 Chapter 2 Pin Functions (11) PCT0 to PCT4 (Port CT) … Input/output Port CT is a 5-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), it operates as control sig- nal output when memory is expanded externally and segment signal output of LCD controller/driver.
Page 45 Chapter 2 Pin Functions (12) PCM0 to PCM1 (Port CM) … Input/output Port CM is a 2-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), it operates as control sig- nal output when memory is expanded externally and segment signal output of LCD controller/driver.
Page 46 Chapter 2 Pin Functions (13) ANI00 to ANI11 (Analog input) … Input These are analog input pins to the A/D converter. (14) COM0 to COM1 (Common signal)... Output These are the common signal output of LCD-controller/driver (15) CLKSEL (Clock generator operating mode select) … Input This is the input pin that specifies the operation mode of the clock generator.
Page 47 Chapter 2 Pin Functions (23) CV (Ground for clock generator) This is the ground pin for the clock generator. (24) V to V (LCD driver supply) LCD0 LCD2 These are the positive power supply pins for the LCD controller/driver. (25) V to V (Power supply) DD50...
Page 48: Types Of Pin I/O Circuit And Connection Of Unused Pin
Chapter 2 Pin Functions 2.3 Types of Pin I/O Circuit and Connection of Unused Pin I/O Circuit Recommended Connection Type CRXD1 For input: individually connect to V or V via a resistor. CTXD1 For output: leave open. CRXD2 CTXD2 CRXD3 CTXD3 RXD1 TXD1...
Page 49 Chapter 2 Pin Functions I/O Circuit Recommended Connection Type PAL0 SEG23 17-G For input: individually connect to V or V via a resistor. PAL1 SEG22 For output: leave open. PAL2 SEG21 PAL3 SEG20 PAL4 SEG19 PAL5 SEG18 PAL6 SEG17 PAL7 SEG16 PAL8 SEG15...
Page 50 Chapter 2 Pin Functions I/O Circuit Recommended Connection Type PDL0 For input: individually connect to V or V via a resistor. PDL1 For output: leave open. PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 AIN0-AIN11 Individually connect to AV or AV...
Page 51: Figure 2-1: Pin I/O Circuits
Chapter 2 Pin Functions Figure 2-1: Pin I/O Circuits Type1 Type 7 P-ch P-ch N-ch & N-ch Type 2 Type 17-G data P-ch IN/OUT output N-ch disable input enable P-ch Type 5-K VLC0 P-ch VLC1 N-ch data P-ch P-ch IN/OUT SEG data output N-ch...
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Page 53: Chapter 3 Cpu Function
Chapter 3 CPU Function The CPU of the V850E/CA1 / ATOMIC is based on a RISC architecture and executes almost all the instructions in one clock cycle, using a 5-stage pipeline control. 3.1 Features • Minimum instruction cycle: 50 ns (@ internal 20 MHz operation) •...
Page 54: Cpu Register Set
Chapter 3 CPU Function 3.2 CPU Register Set The registers of the V850E/CA1 / ATOMIC can be classified into two categories: a general program reg- ister set and a dedicated system register set. All the registers are 32-bit width. For details, refer to V850E User’s Manual Architecture. Figure 3-1: CPU Register Set (1) Program register set (2) System register set...
Page 55: Program Register Set
Chapter 3 CPU Function 3.2.1 Program register set The program register set includes general registers and a program counter. General registers Thirty-two general registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers.
Page 56: System Register Set
Chapter 3 CPU Function 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, use the system register load/store instruction (LDSR or STSR instruction) with a specific system register number indicated below. Table 3-2: System Register Numbers System Register Name Operand Specification...
Page 57: Figure 3-4: Program Status Word (Psw)
Chapter 3 CPU Function Figure 3-4: Program Status Word (PSW) After reset 00000020H Bit Position Flag Function 31 to 8 Reserved field (fixed to 0). Indicates that non-maskable interrupt (NMI) processing is in progress. This flag is set when NMI is accepted, and disables multiple interrupts. 0: NMI servicing not under execution.
Page 58: Operation Modes
Chapter 3 CPU Function 3.3 Operation Modes 3.3.1 Operation modes The V850E/CA1 / ATOMIC has the following operations modes. Mode specification is carried out by the MODE0 to MODE3 pins. Normal operation mode (a) Single-chip mode Access to the internal ROM is enabled. In single-chip mode 0, after system reset is cleared, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal ROM, and instruc- tion processing starts.
Page 59: Operation Mode Specification
Chapter 3 CPU Function 3.3.2 Operation mode specification The operation mode is specified according to the status of pins MODE0 to MODE3. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation.
Page 60: Address Space
Chapter 3 CPU Function 3.4 Address Space 3.4.1 CPU address space The CPU of the V850E/CA1 / ATOMIC is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported.
Page 61: Image
Chapter 3 CPU Function 3.4.2 Image 64 MB physical address space is seen as 64 images in the 4 GB CPU address space. In actuality, the same 64 MB physical address space is accessed regardless of the values of bits 31 to 26 of the CPU address.
Page 62: Wrap-Around Of Cpu Address Space
Chapter 3 CPU Function 3.4.3 Wrap-around of CPU address space Program space Of the 32 bits of the PC (program counter), the higher 6 bits are set to “0”, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calcula- tion, the higher 6 bits ignore the carry or borrow.
Page 63: Memory Map
Chapter 3 CPU Function 3.4.4 Memory map The V850E/CA1 / ATOMIC reserves areas as shown in Figure 3-9. Each mode is specified by the MODE0 to MODE3 pins. Figure 3-9: Memory Map (µPD703123, 703F123) Single-chip mode x3FFFFFFH Internal peripheral 4 Kbytes I/O area x3FFF000H x3FFEFFFH...
Page 64: Area
Chapter 3 CPU Function 3.4.5 Area Internal ROM area (a) Memory map (µPD703123, 70F3123) 1 MB of internal ROM area, addresses 00000H to FFFFFH, is reserved. <1> µPD703123 256 KB are provided in the following addresses as physical internal ROM (mask ROM). •...
Page 65 Chapter 3 CPU Function Table 3-3: Interrupt/Exception Table (1/2) Start Address of Interrupt/ Interrupt/Exception Source Exception Table 00000000H RESET 00000010H NMIVC 00000020H INTWDT 00000040H TRAP0n (n = 0 to F) 00000050H TRAP1n (n = 0 to F) 00000060H ILGOP/DBTRAP 00000080H CINTLPOW 00000090H AD/INTDET...
Page 66 Chapter 3 CPU Function Table 3-3: Interrupt/Exception Table (2/2) Start Address of Interrupt/ Interrupt/Exception Source Exception Table 000002D0H CAN1TRX 000002E0H CAN1ERR 000002F0H CAN2REC 00000300H CAN2TRX 00000310H CAN2ERR 00000320H CAN3REC 00000330H CAN3TRX 00000340H CAN3ERR 00000350H INTCSI0 00000360H INTCSI1 00000370H INTSER0 00000380H INTSR0 00000390H INTST0...
Page 67: Figure 3-10: Internal Ram Area
Chapter 3 CPU Function Figure 3-10: Internal RAM Area µPD703123, µPD70F3123 3FFEFFFH 3FFE800H 3FFE7FFH Internal RAM area (10 Kbytes) 3FFC000H Internal peripheral I/O area 4 KB of memory, addresses 3FFF000H to 3FFFFFFH, is provided as an internal peripheral I/O area. Figure 3-11: Internal Peripheral I/O Area 3FFFFFFH Internal peripheral I/O area...
Page 68: External Memory Expansion
Chapter 3 CPU Function External memory area The following areas can be used as external memory area. (a) µPD703123, 70F3123 x0100000H to xFFFBFFFH Access to the external memory area uses the chip select signal assigned to each memory block (which is carried out in the CS unit set by chip area selection control registers 0 and 1 (CSC0, CSC1)).
Page 69: Figure 3-12: Example Application Of Wrap-Around (Μpd703123)
Chapter 3 CPU Function Figure 3-12: Example Application of wrap-around (µPD703123) 0001FFFFH 00007FFFH Internal ROM area 32 Kbytes (R=) 00000000H Internal peripheral 4 Kbytes I/O area FFFFF000H FFFFEFFFH FFFFE800H FFFFE7FFH Internal RAM area 10 Kbytes FFFFC000H FFFFBFFFH External memory 16 Kbytes area FFFFA000H When R = r0 (zero register) is specified with the LD/ST disp16 [R] instruction, an addressing range...
Page 70: Figure 3-13: Recommended Memory Map
Chapter 3 CPU Function Figure 3-13: Recommended Memory Map Data space FFFFFFFFH FFFFFA28H FFFFFA27H Internal peripheral I/O FFFFF000H FFFFEFFFH xFFFFFFFH Internal RAM xFFFFA28H FFFFC000H xFFFFA27H FFFFBFFFH Internal peripheral I/O xFFFF000H xFFFEFFFH xFFFE800H xFFFE7FFH Internal RAM xFFFC000H 04000000H xFFFFBFFFH 03FFFFFFH Internal Note peripheral I/O 03FFF000H...
Page 71: Peripheral I/O Registers
Chapter 3 CPU Function 3.4.8 Peripheral I/O registers Table 3-4: List of Peripheral I/O Registers (Sheet 1 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFFF000H Port AL Undefined ×...
Page 72 Chapter 3 CPU Function Table 3-4: List of Peripheral I/O Registers (Sheet 2 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × × FFFFF06EH System wait control register VSWC ×...
Page 73 Chapter 3 CPU Function Table 3-4: List of Peripheral I/O Registers (Sheet 3 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × × FFFFF110H Interrupt control register PIC0 × ×...
Page 74 Chapter 3 CPU Function Table 3-4: List of Peripheral I/O Registers (Sheet 4 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × × FFFFF166H Interrupt control register PIC43 × ×...
Page 75 Chapter 3 CPU Function Table 3-4: List of Peripheral I/O Registers (Sheet 5 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × × FFFFF420H Port1 mode × × FFFFF422H Port2 mode ×...
Page 76 Chapter 3 CPU Function Table 3-4: List of Peripheral I/O Registers (Sheet 6 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFFF654H Secondary Capture/Compare Regis- CVSE20 0000H ter of Subchannel 2 ×...
Page 77 Chapter 3 CPU Function Table 3-4: List of Peripheral I/O Registers (Sheet 7 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFFF69CH Secondary Capture/Compare Regis- CVSE41 0000H ter of Subchannel 4 ×...
Page 78 Chapter 3 CPU Function Table 3-4: List of Peripheral I/O Registers (Sheet 8 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFFF6E4H Timebase Status Register TBSTATE2 R/(W) 0000H ×...
Page 79 Chapter 3 CPU Function Table 3-4: List of Peripheral I/O Registers (Sheet 9 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × × × FFFFF892H Filter edge mode channel 21 FEM21 ×...
Page 80 Chapter 3 CPU Function Table 3-4: List of Peripheral I/O Registers (Sheet 10 of 10) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits × FFFFFA03H UART reception error status register ASIS0 ×...
Page 81: Programmable Peripheral I/O Registers
Chapter 3 CPU Function 3.4.9 Programmable peripheral I/O registers In the V850E/CA1, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O area. In this area, the area between x0000H and x0FFFH is used exclusively for the FCAN controller. The internal bus of the V850E/CA1 becomes active when the peripheral I/O register area (FFFF000H to FFFFFFFH) or the programmable peripheral I/O register area (xxxxm000H to xxxxnFFFH) is accessed (m = xx00B, n = xx11B).
Page 82: Figure 3-15: Peripheral Area Selection Control Register (Bpc)
Chapter 3 CPU Function Peripheral area selection control register (BPC) This register can be read/written in 16-bit units. Figure 3-15: Peripheral Area Selection Control Register (BPC) Address Initial value BPC PA15 PA13 PA12 PA11 PA10 PA9 PA0 FFFFF064H 0000H Bit Position Bit Name Function PA15...
Page 83: Table 3-5: List Of Programmable Peripheral I/O Registers (Sheet 1 Of 32)
Chapter 3 CPU Function A list of the programmable peripheral I/O registers is shown below: Table 3-5: List of programmable peripheral I/O registers (Sheet 1 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn000H...
Page 84 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 2 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn041H CAN message event pointer 021 M_EVT021 Undefined xxxxn042H CAN message event pointer 022...
Page 85 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 3 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn084H CAN message data length register 04 M_DLC04 Undefined xxxxn085H...
Page 86 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 4 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn0C8H CAN message data register 060 M_DATA060 R/W Undefined xxxxn0C9H CAN message data register 061...
Page 87 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 5 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn10BH CAN message data register 083 M_DATA083 R/W Undefined xxxxn10CH CAN message data register 084...
Page 88 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 6 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn14EH CAN message data register 106 M_DATA106 R/W Undefined xxxxn14FH CAN message data register 107...
Page 89 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 7 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn192H CAN message ID register H12 M_IDH12 Undefined xxxxn194H CAN message configuration register 12 M_CONF12 R/W...
Page 90 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 8 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn1D6H CAN status set/cancel register 14 SC_STAT14 W 0000H xxxxn1E0H CAN message event pointer 150...
Page 91 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 9 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn222H CAN message event pointer 172 M_EVT172 Undefined xxxxn223H CAN message event pointer 173...
Page 92 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 10 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn265H CAN message control register 19 M_CTRL19 Undefined xxxxn266H CAN message time stamp register 19...
Page 93 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 11 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn2A9H CAN message data register 211 M_DATA211 R/W Undefined xxxxn2AAH CAN message data register 212...
Page 94 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 12 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn2ECH CAN message data register 234 M_DATA234 R/W Undefined xxxxn2EDH CAN message data register 235...
Page 95 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 13 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn32FH CAN message data register 257 M_DATA257 R/W Undefined xxxxn330H CAN message ID register L25...
Page 96 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 14 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn374H CAN message configuration register 27 M_CONF27 R/W Undefined xxxxn375H CAN message status register 27...
Page 97 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 15 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn3C0H CAN message event pointer 300 M_EVT300 Undefined xxxxn3C1H CAN message event pointer 301...
Page 98 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 16 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn403H CAN message event pointer 323 M_EVT323 Undefined xxxxn404H CAN message data length register 32...
Page 99 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 17 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn446H CAN message time stamp register 34 M_TIME34 Undefined xxxxn448H...
Page 100 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 18 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn48AH CAN message data register 362 M_DATA362 R/W Undefined xxxxn48BH CAN message data register 363...
Page 101 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 19 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn4CDH CAN message data register 385 M_DATA385 R/W Undefined xxxxn4CEH CAN message data register 386...
Page 102 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 20 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn510H CAN message ID register L40 M_IDL40 Undefined xxxxn512H CAN message ID register H40...
Page 103 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 21 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn555H CAN message status register 42 M_STAT42 Undefined xxxxn556H CAN status set/cancel register 42...
Page 104 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 22 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn5A1H CAN message event pointer 451 M_EVT451 Undefined xxxxn5A2H CAN message event pointer 452...
Page 105 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 23 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn5E4H CAN message data length register 47 M_DLC47 Undefined Xxxxn5E5H...
Page 106 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 24 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn628H CAN message data register 490 M_DATA490 R/W Undefined xxxxn629H CAN message data register 491...
Page 107 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 25 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn66BH CAN message data register 513 M_DATA513 R/W Undefined xxxxn66CH CAN message data register 514...
Page 108 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 26 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn6AEH CAN message data register 536 M_DATA536 R/W Undefined xxxxn6AFH CAN message data register 537...
Page 109 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 27 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn6F2H CAN message ID register H55 M_IDH55 Undefined xxxxn6F4H CAN message configuration register 55 M_CONF55 R/W...
Page 110 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 28 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn736H CAN status set/cancel register 57 SC_STAT57 W 0000H xxxxn740H CAN message event pointer 580...
Page 111 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 29 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn782H CAN message event pointer 602 M_EVT602 Undefined xxxxn783H CAN message event pointer 603...
Page 112 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 30 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn7C5H CAN message control register 62 M_CTRL62 Undefined xxxxn7C6H CAN message time stamp register 62...
Page 113 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 31 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn812H CAN global interrupt enable register CGIE 0A00H Note xxxxn814H...
Page 114 Chapter 3 CPU Function Table 3-5: List of programmable peripheral I/O registers (Sheet 32 of 32) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 bit 8 bits 16 bits xxxxn89EH CAN2 synchronization control register C2SYNC 0218H xxxxn8C0H CAN1 address mask register L0 C3MASKL0...
Page 115: Specific Registers
Chapter 3 CPU Function 3.5 Specific Registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, it is notified by the peripheral status register (PHS). The V850E/ CA1 has three specific registers, clock control register (CKC), the power save control register (PSC) and the power save mode register (PSM).
Page 116: Command Register (Prcmd)
Chapter 3 CPU Function 3.5.1 Command Register (PRCMD) This command register (PRCMD) is to protect the registers that may have a significant influence on the application system (PSC, PSM) from an inadvertent write access, so that the system does not stop in case of a program hang-up.
Page 117: Peripheral Status Register (Phs)
Chapter 3 CPU Function 3.5.3 Peripheral Status Register (PHS) The flag PRERR in the peripheral status register PHS indicates protection error occurrence. This register can be read/written in 8-bit units or bit-wise. Address At Reset PRERR FFFFF802H Protection error detection: If an incorrect write operation in a sequence without accessing the command register is performed to a protected internal register, the register is not written to, causing a protection error.
Page 118: Internal Peripheral Function Wait Control Register Vswc
Chapter 3 CPU Function 3.5.4 Internal peripheral function wait control register VSWC This register inserts wait states to the internal access of peripheral SFRs. This register can be read or written in 1-bit and 8-bit units. Address Reset Value VSWC SUWL2 SUWL1 SUWL0...
Page 119: Chapter 4 Bus Control Function
Chapter 4 Bus Control Function The V850E/CA1 / ATOMIC is provided with an external bus interface function by which external memo- ries such as ROM and RAM, and I/O can be connected. 4.1 Features • 16-bit/8-bit data bus sizing function •...
Page 120: Memory Block Function
Chapter 4 Bus Control Function 4.3 Memory Block Function The 64 MB memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB units. Figure 4-1: Memory Block Function 3FFFFFFH 3FFFFFFH Block 15 Internal peripheral I/O area (4 Kbytes) (2 Mbytes) 3E00000H 3FFF000H...
Page 121: Chip Select Control Function
Chapter 4 Bus Control Function 4.3.1 Chip Select Control Function The 64 MB memory area can be divided into 2 MB, 4 MB and 8 MB memory blocks by the chip area selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signals. The memory area can be effectively used by dividing the memory area into memory blocks using the chip select control function.
Page 122 Chapter 4 Bus Control Function Figure 4-2: Chip Area Select Control Registers 0, 1 (2/2) Bit Position Bit Name Function 15 to 0 CSn0 to Chip Select CSn3 Enables chip select. (n = 0 to 7) CSnm CS Operation CS00 CS0 active during block 0 access CS01 CS0 active during block 1 access.
Page 123: Bus Cycle Type Control Function
Chapter 4 Bus Control Function 4.4 Bus Cycle Type Control Function In the V850E/CA1 / ATOMIC, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O • Page ROM Connected external devices are specified by the bus cycle type configuration registers 0, 1 (BCT0, BCT1).
Page 124: Bus Access
Chapter 4 Bus Control Function 4.5 Bus Access 4.5.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Table 4-1: Number of Bus Access Clocks Resources (Bus width) Internal ROM Internal RAM Peripheral I/O External memory (32 bits)
Page 125: Endian Control Function
Chapter 4 Bus Control Function 4.5.3 Endian control function The endian control function can be used to set processing of word data in memory either by the Big Endian method or the Little Endian method for each CS area selected with the chip select signal (CS0 to CS7).
Page 126: Bus Width
Chapter 4 Bus Control Function 4.5.4 Bus width The V850E/CA1 / ATOMIC accesses peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. Access all data in order starting from the lower order side.
Page 127 Chapter 4 Bus Control Function (c) When the data bus width is 16 bits (Big Endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 2n + 1 Byte data External Byte data External data bus data bus...
Page 128 Chapter 4 Bus Control Function Halfword access (16 bits) (a) When the bus width is 16 bits (Little Endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1-st Access 2-nd Access Address Address Address 2n + 1 2n + 1 2n + 2...
Page 129 Chapter 4 Bus Control Function (c) When the data bus width is 16 bits (Big Endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1-st Access 2-nd Access Address Address Address 2n + 2 2n + 1 2n + 1 Halfword...
Page 130 Chapter 4 Bus Control Function Word access (32 bits) (a) When the bus width is 16 bits (Little Endian) <1> Access to address 4n 1-st Access 2-nd Access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data External...
Page 131 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data External data bus data bus <4>...
Page 132 Chapter 4 Bus Control Function (b) When the bus width is 8 bits (Little Endian) <1> Access to address 4n 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data...
Page 133 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External...
Page 134 Chapter 4 Bus Control Function (c) When the data bus width is 16 bits (Big Endian) <1> Access to address 4n 1-st Access 2-nd Access Address Addres 4n + 2 4n + 1 4n + 3 Word data External Word data External data bus data bus...
Page 135 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access Address Address 4n + 2 4n + 4 4n + 3 4n + 5 Word data External Word data External data bus data bus <4>...
Page 136 Chapter 4 Bus Control Function (d) When the data bus width is 8 bits (Big Endian) <1> Access to address 4n 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data...
Page 137 Chapter 4 Bus Control Function <3> Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External...
Page 138: Wait Function
Chapter 4 Bus Control Function 4.6 Wait Function 4.6.1 Programmable wait function Data wait control registers 0, 1 (DWC0, DWC1) With the purpose of realizing easy interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states with respect to the starting bus cycle for each CS area. The number of wait states can be specified by data wait control registers 0 and 1 (DWC0, DWC1) in programming.
Page 139 Chapter 4 Bus Control Function Address setup wait control register (ASC) The V850E/CA1 / ATOMIC allows insertion of address setup wait states before the T1 cycle of the SRAM or page ROM cycle. The number of address setup wait states can be set with the ASC register for each CS area. This register can be read/written in 16-bit units.
Page 140: External Wait Function
Chapter 4 Bus Control Function 4.6.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by the external wait pin (WAIT) to synchronize with the external device. Just as with programmable waits, access to internal ROM, internal RAM, and internal peripheral I/O areas cannot be controlled by external waits.
Page 141: Idle State Insertion Function
Chapter 4 Bus Control Function 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the cur- rent bus cycle after the T2 state to meet the data output float delay time (tdf) on memory read access for each CS space.
Page 142: Bus Priority Order
Chapter 4 Bus Control Function 4.8 Bus Priority Order There are three external bus cycles: DMA cycle, operand data access, and instruction fetch. As for the priority order, the highest priority has the DMA cycle, instruction fetch, and operand data access, in this order.
Page 143: Boundary Operation Conditions
Chapter 4 Bus Control Function 4.9 Boundary Operation Conditions 4.9.1 Program space (1) Branching to the peripheral I/O area or successive fetch from the internal RAM area to the internal peripheral I/O area is inhibited. In terms of hardware, fetching the NOP op code continues, and fetching from the external memory is not performed.
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Page 145: Chapter 5 Memory Access Control Function
Chapter 5 Memory Access Control Function 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features • Access to SRAM takes a minimum of 2 states. • Up to 7 states of programmable data waits can be inserted through setting of the DWC0 and DWC1 registers.
Page 146: Sram Connections
Chapter 5 Memory Access Control Function 5.1.2 SRAM connections An example of connection to SRAM is shown below. Figure 5-1: Example of Connection to SRAM (a) When data bus width is 16 bits A1 to A17 A1 to A17 D0 to D15 D1 to D16 2-Mbit SRAM V850E/CA1...
Page 147: Sram, External Rom, External I/O Access
Chapter 5 Memory Access Control Function 5.1.3 SRAM, external ROM, external I/O access Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/6) (a) During read CLKOUT (output) Address Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data...
Page 148 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (2/6) (b) During read (address setup wait, idle state insertion) TASW CLKOUT (output) Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data WAIT (input)
Page 149 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (3/6) (c) During write CLKOUT (output) Address Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data Data WAIT (input) Remarks: 1.
Page 150 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (4/6) (d) During write (address setup wait, idle state insertion) TASW CLKOUT (output) Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) D0 to D15 (I/O) Data WAIT (input)
Page 151 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (5/6) (e) When read → write operation CLKOUT (output) Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) Data Data D0 to D15 (I/O) WAIT (input) Remarks: 1.
Page 152 Chapter 5 Memory Access Control Function Figure 5-2: SRAM, External ROM, External I/O Access Timing (6/6) (f) When write → read operation CLKOUT (output) Address A0 to A23 (output) CSn (output) RD (output) UWR (output) LWR (output) Data D0 to D15 (I/O) Data WAIT (input) Remarks: 1.
Page 153: Page Rom Controller (Romc)
Chapter 5 Memory Access Control Function 5.2 Page ROM Controller (ROMC) The page ROM controller (ROMC) is provided for access to ROM (page ROM) with the page access function. Comparison of addresses with the immediately preceding bus cycle is carried out and wait control for normal access (off-page) and page access (on-page) is executed.
Page 154: Page Rom Connections
Chapter 5 Memory Access Control Function 5.2.2 Page ROM connections Examples of page ROM connections are shown below. Figure 5-3: Example of Page ROM Connections (a) In case of 16-bit data bus width A1 to A20 A0 to A19 D0 to D15 O1 to O16 V850E/CA1 16-Mbit page ROM...
Page 155: On-Page/Off
Chapter 5 Memory Access Control Function 5.2.3 On-page/off-page judgment Whether a page ROM cycle is on-page or off-page is judged by latching the address of the previous cycle and comparing it with the address of the current cycle. Through the page ROM configuration register (PRC), according to the configuration of the connected page ROM and the number of continuously readable bits, one of the addresses (A3 to A5) is set as the masking address (no comparison is made).
Page 156 Chapter 5 Memory Access Control Function Figure 5-4: On-Page/Off-Page Judgment during Page ROM Connection (2/2) (c) In case of 32-Mbit (2 M × 16 bits) page ROM (16-word page access) Internal address latch (immediately preceding address) PRC register setting Comparison V850E/CA1 address output Page ROM address...
Page 157: Page Rom Configuration Register (Prc)
Chapter 5 Memory Access Control Function 5.2.4 Page ROM configuration register (PRC) This register specifies whether page ROM on-page access is enabled or disabled. If on-page access is enabled, the masking address (no comparison is made) out of the addresses (A3 to A6) corresponding to the configuration of the page ROM being connected to and the number of bits that can be read con- tinuously, as well as the number of waits corresponding to the internal system clock, are set.
Page 158: Page Rom Access
Chapter 5 Memory Access Control Function 5.2.5 Page ROM access Figure 5-6: Page ROM Access Timing (1/4) (a) During read (when half word/word access with 8-bit bus width or when word access with 16-bit bus width) CLKOUT (output) Off-page address On-page address A0 to A23 (output) CSn (output)
Page 159 Chapter 5 Memory Access Control Function Figure 5-6: Page ROM Access Timing (2/4) (b) During read (when byte access with 8-bit bus width or when byte/half word access with 16- bit bus width) CLKOUT (output) Off-page address On-page address A0 to A23 (output) CSn (output) RD (output) UWR (output)
Page 160 Chapter 5 Memory Access Control Function Figure 5-6: Page ROM Access Timing (3/4) (c) During read (address setup wait, idle state insertion) (when half word/word access with 8- bit bus width or when word access with 16-bit bus width) TASW TASW CLKOUT (output) Off-page address...
Page 161 Chapter 5 Memory Access Control Function Figure 5-6: Page ROM Access Timing (4/4) (d) During read (address setup wait, idle state insertion) (when byte access with 8-bit bus width or when byte/half word access with 16-bit bus width) TASW TASW CLKOUT (output) Off-page address On-page address...
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Page 163: Chapter 6 Dma Functions (Dma Controller)
Chapter 6 DMA Functions (DMA Controller) The V850E/CA1 / ATOMIC includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O or among I/Os, based on DMA requests issued by the on-chip peripheral I/O, or software triggers (memory refers to internal RAM).
Page 164: Configuration
Chapter 6 DMA Functions (DMA Controller) 6.2 Configuration Figure 6-1: Block Diagram of DMA Controller Configuration On-chip Internal RAM peripheral I/O Internal bus On-chip peripheral I/O bus DMA source address Data Address register (DSAHn/DSALn) control control DMA destination address register (DDAHn/DDALn) DMA transfer count Count register (DBCn)
Page 165: Control Registers
Chapter 6 DMA Functions (DMA Controller) 6.3 Control Registers 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA source addresses (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAHn and DSALn. Since these registers are configured as 2-stage FIFO buffer registers, a new source address for DMA transfer can be specified during DMA transfer.
Page 166: Figure 6-3: Dma Source Address Registers L0 To L3 (Dsal0 To Dsal3)
Chapter 6 DMA Functions (DMA Controller) DMA source address registers L0 to L3 (DSAL0 to DSAL3) These registers can be read/written in 16-bit units. Figure 6-3: DMA Source Address Registers L0 to L3 (DSAL0 to DSAL3) Address Initial value DSAL0 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF080H undef.
Page 167: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
Chapter 6 DMA Functions (DMA Controller) 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA destination address (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAHn and DDALn. Since these registers are configured as 2-stage FIFO buffer registers, a new destination address for DMA transfer can be specified during DMA transfer.
Page 168: Figure 6-5: Dma Destination Address Registers L0 To L3 (Ddal0 To Ddal3)
Chapter 6 DMA Functions (DMA Controller) DMA destination address registers L0 to L3 (DDAL0 to DDAL3) These registers can be read/written in 16-bit units. Figure 6-5: DMA Destination Address Registers L0 to L3 (DDAL0 to DDAL3) Address Initial value DDAL0 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF084H undef.
Page 169: Dma Transfer Count Registers 0 To 3 (Dbc0 To Dbc3)
Chapter 6 DMA Functions (DMA Controller) 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the transfer counts for DMA channels n (n = 0 to 3). They store the remaining transfer counts during DMA transfer. Since these registers are configured as 2-stage FIFO buffer registers, a new DMA transfer count for DMA transfer can be specified during DMA transfer.
Page 170: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
Chapter 6 DMA Functions (DMA Controller) 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer modes for DMA channel n (n = 0 to 3). These registers cannot be accessed during DMA operation. They can be read/written in 16-bit units.
Page 171: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
Chapter 6 DMA Functions (DMA Controller) 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only.
Page 172: Dma Disable Status Register (Ddis)
Chapter 6 DMA Functions (DMA Controller) 6.3.6 DMA disable status register (DDIS) This register holds the contents of the ENn bit of the DCHCn register during NMI input (n = 0 to 3). This register is read-only in 8-bit or 1-bit units. Figure 6-9: DMA Disable Status Register (DDIS) Address Initial...
Page 173: Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3)
Chapter 6 DMA Functions (DMA Controller) 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors. These registers can be read/written in 8-bit/1-bit units.
Page 174 Chapter 6 DMA Functions (DMA Controller) Figure 6-11: DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3) (2/3) Bit Posi- Bit Name Function tion 5 to 0 IFC5 to Sets the interrupt source that serves as the DMA start factor. IFC0 IFC5 IFC4 IFC3 IFC2 IFC1 IFC0 Interrupt Source...
Page 175 Chapter 6 DMA Functions (DMA Controller) Figure 6-11: DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3) (3/3) Bit Posi- Bit Name Function tion 5 to 0 IFC5 to Sets the interrupt source that serves as the DMA start factor. IFC0 IFC5 IFC4 IFC3 IFC2 IFC1 IFC0 Interrupt Source...
Page 176: Dma Bus States
Chapter 6 DMA Functions (DMA Controller) 6.4 DMA Bus States 6.4.1 Types of bus states The DMAC bus states consist of the following 8 states. TI state The TI state is an idle state, during which no access request is issued. T0 state DMA transfer ready state (state in which a DMA transfer request has been issued and the bus mas- tership is acquired for the first DMA transfer).
Page 177: Dmac Bus Cycle State Transition
Chapter 6 DMA Functions (DMA Controller) 6.4.2 DMAC bus cycle state transition Except for the block transfer mode, each time the processing for a DMA transfer is completed, the bus mastership is released. Figure 6-12: DMAC Bus Cycle (Two-Cycle Transfer) State Transition T2RI Preliminary User’s Manual U14913EE1V0UM00...
Page 178: Transfer Mode
Chapter 6 DMA Functions (DMA Controller) 6.5 Transfer Mode 6.5.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword/word transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs.
Page 179: Transfer Object
Chapter 6 DMA Functions (DMA Controller) 6.7 Transfer Object 6.7.1 Transfer type and transfer object Table 6-1 lists the relationships between transfer type and transfer object (√: transfer enabled, ×: trans- fer disabled). Table 6-1: Relationship Between Transfer Type and Transfer Object Destination Two-Cycle Transfer Internal...
Page 180: Next Address Setting Function
Chapter 6 DMA Functions (DMA Controller) 6.9 Next Address Setting Function The DMA source address registers (DSAHn, DSALn), DMA destination address registers (DDAHn, DDALn), and DMA transfer count register (DBCn) are buffer registers with a 2-stage FIFO configuration (n = 0 to 3). When the terminal count is issued, these registers are automatically rewritten with the value that was set immediately before.
Page 181: Dma Transfer Start Factors
Chapter 6 DMA Functions (DMA Controller) 6.10 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. Request from software If the STGn, ENn, and TCn bits of the DCHCn register are set as follows, DMA transfer starts (n = 0 to 3).
Page 182: Dma Transfer End
Chapter 6 DMA Functions (DMA Controller) 6.12 DMA Transfer End 6.12.1 DMA transfer end interrupt When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end inter- rupt (INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3). 6.12.2 Terminal count output upon DMA transfer end The terminal count signal becomes active for one clock during the last DMA transfer cycle.
Page 183: Chapter 7 Interrupt/Exception Processing Function
Chapter 7 Interrupt/Exception Processing Function The V850E/CA1 / ATOMIC is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 62 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 184: Table 7-1: Interrupt/Exception Source List (Sheet 1 Of 3)
Chapter 7 Interrupt/Exception Processing Function Table 7-1: Interrupt/Exception Source List (Sheet 1 of 3) Interrupt/Exception Source Default Exception Handler Restored Type Classification Controlling Generating Priority Code Address Name Generating Source Register Unit Reset Interrupt RESET – RESET input – 0000H 00000000H Undefined Non-maskable...
Page 185 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Interrupt/Exception Source List (Sheet 2 of 3) Interrupt/Exception Source Default Exception Handler Restored Type Classification Controlling Generating Priority Code Address Name Generating Source Register Unit Maskable Interrupt TINTCCE41 PIC23 CC coincidence / Pin TimerE1/ 01F0H 000001F0H...
Page 186 Chapter 7 Interrupt/Exception Processing Function Table 7-1: Interrupt/Exception Source List (Sheet 3 of 3) Interrupt/Exception Source Default Exception Handler Restored Type Classification Controlling Generating Priority Code Address Name Generating Source Register Unit Maskable Interrupt INTST1 PIC52 UART1 transmission com- UART1 03C0H 000003C0H nextPC...
Page 187: Non-Maskable Interrupts
Chapter 7 Interrupt/Exception Processing Function 7.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. Non-maskable interrupts of V850E/CA1 / ATOMIC are available for the following two requests: • NMI pin input (NMIVC) •...
Page 188: Operation
Chapter 7 Interrupt/Exception Processing Function 7.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers con- trol to the handler routine: (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010H to the higher halfword (FECC) of ECR.
Page 189: Figure 7-2: Acknowledging Non-Maskable Interrupt Request
Chapter 7 Interrupt/Exception Processing Function Figure 7-2: Acknowledging Non-Maskable Interrupt Request (a) If a new NMIVC request is generated while an NMIVC service program is being executed Main routine (PSW.NP = 1) NMI request held pending because NMI request NMI request PSW.NP = 1 Pending NMI request processed (b) If a new NMIVC request is generated twice while an NMIVC service program is being exe-...
Page 190: Figure 7-3: Example Of Non-Maskable Interrupt Request Acknowledgement Operation (1/2)
Chapter 7 Interrupt/Exception Processing Function Figure 7-3: Example of Non-Maskable Interrupt Request Acknowledgement Operation (1/2) (c) Multiple NMI requests generated at the same time NMIVC and NMIWD requests generated simultaneously Main routine NMIWD servicing NMIVC and NMIWD System reset requests (generated simultaneously) Preliminary User’s Manual U14913EE1V0UM00...
Page 191 Chapter 7 Interrupt/Exception Processing Function Figure 7-3: Example of Non-Maskable Interrupt Request Acknowledgement Operation (2/2) (d) NMI request generated during NMI servicing NMI being NMI request generated during NMI servicing serviced NMIVC NMIWD • NMIVC request generated during • NMIWD request generated NMIVC NMIVC servicing during NMIVC servicing...
Page 192: Restore
Chapter 7 Interrupt/Exception Processing Function 7.2.2 Restore NMIVC Execution is restored from the non-maskable interrupt (NMIVC) processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>Restores the values of the PC and the PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1.
Page 193: Non-Maskable Interrupt Status Flag (Np)
Chapter 7 Interrupt/Exception Processing Function 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execu- tion. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 194: Edge Detection Function
Chapter 7 Interrupt/Exception Processing Function 7.2.4 Edge detection function The behaviour of the non-maskable interrupt (NMIVC) can be specified by the voltage comparator mode register. The valid edge of the external NMI pin input can be specified by the EDN1, EDN0 bits, whereas the source has to be selected by the NSOCE bit.
Page 195: Maskable Interrupts
Chapter 7 Interrupt/Exception Processing Function 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850E/CA1 / ATOMIC has 60 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 196: Figure 7-7: Maskable Interrupt Processing
Chapter 7 Interrupt/Exception Processing Function Figure 7-7: Maskable Interrupt Processing INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 197: Restore
Chapter 7 Interrupt/Exception Processing Function 7.3.2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 198: Priorities Of Maskable Interrupts
Chapter 7 Interrupt/Exception Processing Function 7.3.3 Priorities of maskable interrupts The V850E/CA1 / ATOMIC provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 199: Figure 7-9: Example Of Processing In Which Another Interrupt Request Is Issued
Chapter 7 Interrupt/Exception Processing Function Figure 7-9: Example of Processing in Which Another Interrupt Request Is Issued While an Inter- rupt Is Being Processed (1/2) Main routine Processing of a Processing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the (level 3) (level 2) priority of b is higher than that of a and interrupts are...
Page 200 Chapter 7 Interrupt/Exception Processing Function Figure 7-9: Example of Processing in Which Another Interrupt Request Is Issued While an Inter- rupt Is Being Processed (2/2) Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 201: Figure 7-10: Example Of Processing Interrupt Requests Simultaneously Generated
Chapter 7 Interrupt/Exception Processing Function Figure 7-10: Example of Processing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Processing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 202: Interrupt Control Register (Picn)
Chapter 7 Interrupt/Exception Processing Function 7.3.4 Interrupt control register (PICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the con- trol conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Figure 7-11: Interrupt Control Register (PICn) Address Initial...
Page 203: Table 7-2: Addresses And Bits Of Interrupt Control Registers (Sheet 1 Of 2)
Chapter 7 Interrupt/Exception Processing Function Table 7-2: Addresses and Bits of Interrupt Control Registers (Sheet 1 of 2) Address Register FFFFF110H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF112H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF114H PIC2 PIF2 PMK2 PPR22 PPR21 PPR20 FFFFF116H PIC3...
Page 204 Chapter 7 Interrupt/Exception Processing Function Table 7-2: Addresses and Bits of Interrupt Control Registers (Sheet 2 of 2) Address Register FFFFF166H PIC43 PIF43 PMK43 PPR432 PPR431 PPR430 FFFFF168H PIC44 PIF44 PMK44 PPR442 PPR441 PPR440 FFFFF16AH PIC45 PIF45 PMK45 PPR452 PPR451 PPR450 FFFFF16CH PIC46 PIF46...
Page 205: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
Chapter 7 Interrupt/Exception Processing Function 7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The PMKn bit of the IMR0 to IMR3 registers is equivalent to the PMKn bit of the PICn register. IMRm registers can be read/written in 16-bit units (m = 0 to 3).
Page 206: In-Service Priority Register (Ispr)
Chapter 7 Interrupt/Exception Processing Function 7.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an inter- rupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 207: Noise Elimination Circuit
Chapter 7 Interrupt/Exception Processing Function 7.4 Noise Elimination Circuit V850E/CA1 / ATOMIC is provided with filter / edge detection circuits for ports 3, 4, 5 and port 6 (3 chan- nels). The circuit consists from programmable digital filter, analog filter, edge detection and input source selection.
Page 208: Analog Filter
Chapter 7 Interrupt/Exception Processing Function Figure 7-16: Port Interrupt Input Circuit Overview Filter Digital Filter Frequencies Clock Clock 0 Clock 1 Clock 2 TINTCCEm0 from Timer E0 INTPn Analog to Interrupt Filter Edge Input INTPn Controller Detection EDGEM1, DFEN EDGEM0 Digital Filter FSMP1,...
Page 209: Digital Filter
Chapter 7 Interrupt/Exception Processing Function 7.4.2 Digital Filter Behavioral Description The digital filter simply samples the input with the negative clock edge of the f internal system clock. The negative clock edge is used to suppress the sampling of glitches caused by the V850E/CA1 / ATOMIC hardware and its external circuitry itself (assuming that all outputs from the V850E/CA1 / ATOMIC change their values only on positive edges of the f clock or any derived sub-clock).
Page 210: Interrupt Trigger Mode Selection
Chapter 7 Interrupt/Exception Processing Function 7.4.3 Interrupt trigger mode selection The valid edge of the INTP pins can be selected by program. The edge that can be selected as the valid edge is one of the following. • Rising edge •...
Page 211 Chapter 7 Interrupt/Exception Processing Function Figure 7-18: Timer E Input Pin Filter Edge Detect Mode Registers (FEM0n to FEM5n) (n=0 to 2) (2/2) Bit Name Description DFEN Digital filter enable Selects analog or digital filter for interrupt input. 0: Analog filter 1: Digital filter Note: Refer to Figure 7-15: “Timer E Input Circuit Overview”...
Page 212: Filter Edge Detect Mode Register (Fem0N To Fem5N) For Int0, Int1 And Int2 Input Pins
Chapter 7 Interrupt/Exception Processing Function 7.4.5 Filter Edge Detect Mode Register (FEM0n to FEM5n) for INT0, INT1 and INT2 Input Pins This registers are 8-bit register that control the analog or digital filter function for the INT2 to INT0 inputs and the edge selection to the dedicated interrupt controller.
Page 213: Software Exception
Chapter 7 Interrupt/Exception Processing Function 7.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 7.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to EIPC.
Page 214: Restore
Chapter 7 Interrupt/Exception Processing Function 7.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. (1) Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW.
Page 215: Exception Status Flag (Ep)
Chapter 7 Interrupt/Exception Processing Function 7.5.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Figure 7-22: Exception Status Flag (EP) 8 7 6 5 4 3 2 1 0 Initial value...
Page 216: Exception Trap
Chapter 7 Interrupt/Exception Processing Function 7.6 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. In the V850E/CA1 / ATOMIC, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is consid- ered as an exception trap.
Page 217: Figure 7-24: Restore Processing From Exception Trap
Chapter 7 Interrupt/Exception Processing Function Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 218: Debug Trap
Chapter 7 Interrupt/Exception Processing Function 7.6.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. Operation When the debug trap is generated, the CPU performs the following processing, transfers control to the debug monitor routine, and shifts to debug mode.
Page 219: Figure 7-26: Restore Processing From Debug Trap
Chapter 7 Interrupt/Exception Processing Function Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 220: Multiple Interrupt Processing Control
Chapter 7 Interrupt/Exception Processing Function 7.7 Multiple Interrupt Processing Control Multiple interrupt processing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is received and processed first.
Page 221 Chapter 7 Interrupt/Exception Processing Function Generation of exception in service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register ← Exception such as TRAP instruction acknowledged. • TRAP instruction •...
Page 222: Interrupt Response Time
Chapter 7 Interrupt/Exception Processing Function 7.8 Interrupt Response Time The following table describes the V850E/CA1 / ATOMIC interrupt response time (from interrupt genera- tion to start of interrupt processing). Figure 7-27: Pipeline Operation at Interrupt Request Acknowledgment (Outline) 5 system clocks CLKOUT Interrupt request Instruction 1...
Page 223: Periods In Which Interrupts Are Not Acknowledged
Chapter 7 Interrupt/Exception Processing Function 7.9 Periods in Which Interrupts Are Not Acknowledged An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt non-sample instruction and the next instruction. The interrupt request non-sampling instructions are as follows. •...
Page 224 [MEMO] Preliminary User’s Manual U14913EE1V0UM00...
Page 225: Chapter 8 Clock Generator
Chapter 8 Clock Generator 8.1 Features • Multiplication function by PLL synthesizer: 4 x multiplication • Clock sources - Oscillation through oscillator connection - External clock input • Power save modes - Watch mode - HALT mode - IDLE mode - STOP mode •...
Page 226: Main System Clock Oscillator
Chapter 8 Clock Generator 8.3 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or ceramic resonator connected to the X1 and X2 pins. Figure 8-2: Main system clock oscillator Preliminary User’s Manual U14913EE1V0UM00...
Page 227: Control Registers
Chapter 8 Clock Generator 8.4 Control Registers 8.4.1 Clock Control Register (CKC) This is a 8-bit register that controls the clock management. Data can be written to it only in a sequence of specific instructions so that its contents are not easily rewritten in case of program hang-up.
Page 228: Pll Status Register (Pstat)
Chapter 8 Clock Generator Start-up after any Power-Save Mode condition recommendation It is recommended to proceed in the following way when performing power-save functions: 1. Switch off the PLL (PLLEN bit of CKC) 2. Wait for “PLL switch off status” by reading VBSTAT bit in PSTAT register. 3.
Page 229: Table 8-2: Relation System Clock To Resonator Frequency
Chapter 8 Clock Generator Available clock frequencies in the OSC mode: Table 8-2: Relation system clock to resonator frequency System clock frequency (f System clock frequency (f Frequency of external resonator PLL On PLL Off 20.000 MHz 5.0000 MHz 5.0000 MHz 16.000 MHz 4.0000 MHz 4.0000 MHz...
Page 230: Power Saving Functions
Chapter 8 Clock Generator 8.5 Power Saving Functions 8.5.1 General The device provides the following power saving functions. These modes can be combined and switched to suit the target application, which enables effective implementation of low-power systems. Table 8-4: Power Saving Modes Overview Clock Source Mode Operation of...
Page 231: Figure 8-3: Power Save Mode State Transition Diagram
Chapter 8 Clock Generator Figure 8-3 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, WATCH mode, and software STOP mode. An effective low power consumption system can be realized by combining these modes and switching modes according to the required use.
Page 232: Table 8-5: Power Saving Mode Frequencies
Chapter 8 Clock Generator Table 8-5: Power Saving Mode Frequencies Clock Source Mode Operation of Clock Supply to oscillator peripherals watch/ prescaler watch- prescaler Initial Status Normal – 4 MHz 4 MHz 4 MHz / 4 MHz / mode PLL enabled Normal 16 MHz 16 MHz...
Page 233: Power Save Modes Outline
Chapter 8 Clock Generator 8.5.2 Power Save Modes Outline V850E/CA1 / ATOMIC is provided with the following standby modes: HALT, IDLE, WATCH, and software STOP. Application systems, which are designed so that these modes are switched appropriately according to operation purposes, reduce power consumption efficiently. HALT mode: In this mode supply of the operating clock to the CPU is stopped whereby other on-chip peripheral functions continue to operate.
Page 234: Halt Mode
Chapter 8 Clock Generator 8.5.3 HALT mode In this mode, the CPU clock is stopped, though the clock generators (oscillator and PLL synthesizer) continue to operate for supplying clock signals to other peripheral function circuits. Setting the HALT mode when the CPU is idle reduces the total system power consumption. In the HALT mode, program execution is stopped but the contents of all registers and internal RAM prior are retained as is.
Page 235: Table 8-7: Operation After Halt Mode Release By Interrupt Request
Chapter 8 Clock Generator HALT mode release: The HALT mode can be released by a non-maskable interrupt request, an unmasked maskable inter- rupt request, or RESET signal input. Release by interrupt request The HALT mode is released unconditionally by an unmasked maskable interrupt request regard- less of its priority level.
Page 236: Idle Mode
Chapter 8 Clock Generator 8.5.4 IDLE Mode In this mode, the CPU clock is stopped resulting in stop of the entire system, though the clock genera- tors (oscillator and PLL synthesizer) continue to operate. As it is not necessary to secure the oscillator oscillation stabilization time and the PLL lock-up time, it is possible to quickly switch to the normal operating mode in response to a release cause.
Page 237: Watch Mode
Chapter 8 Clock Generator 8.5.5 WATCH mode In this mode f clock is stopped while the oscillator continue to operate to achieve low power, though only oscillator & Watch/watchdog timer continue to operate. This mode compensates the HALT modes concerning the oscillator stabilization time and power con- sumption.
Page 238: Table 8-10: Operation After Watch Mode Release By Interrupt Request
Chapter 8 Clock Generator Table 8-10: Operation after WATCH mode release by interrupt request Release cause EI state DI state NMI request Branches to handler address. Maskable interrupt Branches to handler address, or Executes the next instruction. request executes the next instruction. Remark: If WATCH mode is entered during execution of a particular interrupt handler and an unmasked interrupt request with a higher priority than the previous one is subsequently gen- erated, the program branches to the vector address for the later interrupt.
Page 239: Software Stop Mode
Chapter 8 Clock Generator 8.5.6 Software STOP mode In this mode, the CPU clock is stopped including the clock generators (oscillator and PLL synthesizer), resulting in stop of the entire system for ultra-low power consumption (the only consumed is device leakage current).
Page 240: Register Description
Chapter 8 Clock Generator 8.6 Register Description 8.6.1 Power Save Control Register (PSC) This is an 8-bit register that controls the power save mode. Data can be written only in a sequence of specific instructions so that its contents are not easily rewrit- ten in case of program hang-up (see Chapter 3.5 “Specific Registers”...
Page 241 Chapter 8 Clock Generator Data is set in the power save control register (PSC) according to the following sequence. <1> Set the power save mode register (PSM) (with the following instructions). • Store instruction (ST/SST instruction) • Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <2>...
Page 242: Power Save Mode Register (Psm)
Chapter 8 Clock Generator 8.6.2 Power Save Mode Register (PSM) This is a 8-bit register that control the power save mode. This register can be read or written in 8- or 1-bit units. Address At Reset PSM1 PSM0 FFFFF820H Bit name Function PSM1, PSM0 Standby mode specification after STB bit (PSC.1) set to “1”.
Page 243: Securing Oscillation Stabilization Time
Chapter 8 Clock Generator 8.7 Securing Oscillation Stabilization Time 8.7.1 Oscillation stabilization time security specification Two methods can be used to secure the required stabilization times from when watch mode or software STOP mode is released. Securing the time using an on-chip time base counter Watch mode and software STOP mode are released when a valid edge is input to the NMI pin or a maskable interrupt request is input (INTPn).
Page 244: Figure 8-5: Stop Mode Release By Nmi Or Int
Chapter 8 Clock Generator Figure 8-5: STOP mode release by NMI or INT Set software STOP mode Oscillation waveform Internal main clock STOP state NMI (input) Note Oscillator is stopped Time base counter's counting time Note: Valid edge: When specified as the rising edge. The NMI pin should usually be set to an inactive level (for example, high level when the valid edge is specified as the falling edge) in advance.
Page 245: Figure 8-6: Watch Mode Release By Reset Or Watchdog Timer
Chapter 8 Clock Generator Securing the time according to the signal level width (RESET pin input) Watch mode and software STOP mode are released due to falling edge input to the RESET pin. The time until the clock output from the oscillator stabilizes is secured according to the low level width of the signal that is input to the pin.
Page 246: Time Base Counter (Tbc)
Chapter 8 Clock Generator 8.7.2 Time base counter (TBC) The time base counter (TBC) is used to secure the oscillator’s oscillation stabilization time when soft- ware STOP mode is released. It also is used to secure the flash stabilization time when software WATCH mode is released.
Page 247: Chapter 9 Timer / Counter (Real Time Pulse Unit)
Chapter 9 Timer / Counter (Real Time Pulse Unit) 9.1 Timer D 9.1.1 Features (timer D) Timer D (TMD) functions as a 16-bit interval timer. 9.1.2 Function overview (timer D) • 16-bit interval timer: 2 channels • Compare registers: 2 •...
Page 248: Basic Configuration
Chapter 9 Timer / Counter (Real Time Pulse Unit) 9.1.3 Basic configuration Table 9-1: Timer D Configuration List Timer Count Clock Register R/W Generated Capture Timer Other Interrupt Trigger Output S/R Functions Signal Timer D TMD0 – – – – /16, /32, /64,...
Page 249: Figure 9-2: Timer D Registers 0, 1 (Tmd0, Tmd1)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timers D Registers 0, 1 (TMD0, TMD1) TMDn is a 16-bit timer. It is mainly used as an interval timer for software (n = 0, 1). Starting and stopping TMDn is controlled by the CE bit of the timer D control register n (TMCDn). A division by the prescaler can be selected for the count clock from among f /2, f /4, f...
Page 250: Figure 9-3: Timer D Compare Registers 0, 1 (Cmd0 To Cmd1)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer D compare registers 0, 1 (CMD0 to CMD1) CMDn and the TMDn register count value are compared, and an interrupt request signal (TINTCMDn) is generated when a match occurs. TMDn is cleared, synchronized with this match. If the CAE bit of the TMCDn register is set to 0, a reset is performed asynchronously, and the regis- ters are initialized (n = 0, 1).
Page 251: Figure 9-4: Example Of Timing During Tmd Operation
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-4: Example of Timing During TMD Operation (a) When TMDn < CMDn TMDn CMDn TINTCMDn (b) When TMDn > CMDn TMDn FFFFH CMDn INTCMDn Remarks: 1. p = TMDn value when overwritten 2.
Page 252: Control Register
Chapter 9 Timer / Counter (Real Time Pulse Unit) 9.1.4 Control register Timer D control registers 0, 1 (TMCD0 to TMCD1) The TMCDn register controls the operation of timer D (n = 0, 1). This register can be read/written in 8- or 1-bit units. Figure 9-5: Timer D Control Register 0, 1 (TMCD0 to TMCD1) Address I ni t ia l val ue...
Page 253: Operation
Chapter 9 Timer / Counter (Real Time Pulse Unit) 9.1.5 Operation Compare operation TMDn can be used for a compare operation in which the value that was set in a compare register (CMDn) is compared with the TMDn count value (n = 0, 1). If a match is detected by the compare operation, an interrupt (TINTCMDn) is generated.
Page 254: Figure 9-6: Tmd Compare Operation Example
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-6: TMD Compare Operation Example (a) When CMDn is set to m (non-zero) Count clock Count up TMDn clear Clear TMDn CMDn Match detected (TINTCMDn) Remarks: 1. Interval time = (m + 1) × Count clock cycle 2.
Page 255: Application Example
Chapter 9 Timer / Counter (Real Time Pulse Unit) 9.1.6 Application example Interval timer This section explains an example in which timer D is used as an interval timer with 16-bit precision. Interrupt requests (TINTCMDn) are output at equal intervals (refer to Figure 9-6: TMD Compare Operation Example).
Page 256: Timer E
Chapter 9 Timer / Counter (Real Time Pulse Unit) 9.2 Timer E 9.2.1 Features (timer E) The 3 x 6 channels 16/32-bit multi purpose timers En (TMEn) (n = 0 to 2) operate as • Pulse interval and frequency measurement counter •...
Page 257 Chapter 9 Timer / Counter (Real Time Pulse Unit) Note 3, Note 5 Note 2 • Up/down count control with external pin input - Up/down count operation in the compare mode can be controlled with the TCLREn pin input sig- nal.
Page 258: Basic Configuration
Chapter 9 Timer / Counter (Real Time Pulse Unit) 9.2.3 Basic configuration The basic configuration is shown below. Table 9-2: Timer E Configuration List Timer Count Clock Register Generated Capture Trigger Note 1 Other Timer Output Interrupt Functions Signal Timer TBASE0n –...
Page 259: Figure 9-7: Block Diagram Of Timer E
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-7 shows the block diagram of one timer E unit. Figure 9-7: Block Diagram of Timer E CSEn CNT = MAX. TINTOVE0n ECLR 1/2, 1/4, 1/8, 1/16, TBASE0n CNT = 0 TCOUNTE0 1/32, 1/64, 1/128 edge selection...
Page 260: Table 9-3: Meaning Of Signals In Block Diagram
Chapter 9 Timer / Counter (Real Time Pulse Unit) Table 9-3: Meaning of Signals in Block Diagram Signal Name Meaning Note 1 TBASE1n count signal input in 32-bit mode CASC Count value of timer En (CNT = MAX.: Maximum value count signal output of timer En (generated when TBASE0n, TBASE1n = FFFFH), CNT = 0: Zero count signal output of timer (generated when TBASE0n, TBASE1n = 0000H)) TBASE0n, TBASE1n count signal input in 16-bit mode...
Page 261: Figure 9-8: Timer E Time Base Counter 0 Registers 0 To 2 (Tbase00 To Tbase02)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E time base counters 0, 1 registers 0 to 2 (TBASE0n, TBASE1n (n = 0 to 2)) The features of time base counters TBASE0n, TBASE1n are listed below. • Free-running counter that enables counter clearing by compare match of sub-channel 0 and sub- channel 5 •...
Page 262: Figure 9-10: Timer E Sub-Channel 0 Capture/Compare Registers 0 To 2 (Cvse00 To 02)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E sub-channel 0 capture/compare registers 0 to 2 (CVSE00 to CVSE02) The CVSE0n register is the 16-bit sub-channel 0 capture/compare register of timer TMEn (n = 0 to In the capture register mode, it captures the TBASE0n count value. In the compare register mode, it detects match with TBASE0n.
Page 263: Figure 9-11: Timer E Sub-Channel X Main Capture/Compare Registers 0 To 2 (Cvpex0 To Cvpex2) (X = 1 To 4)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E sub-channel x main capture/compare registers 0 to 2 (CVPEx0 to CVPEx2) (x = 1 to 4) The CVPExn register is a 16-bit sub-channel x main capture/compare register of timer TMEn (x = 1 to 4) (n = 0 to 2).
Page 264: Figure 9-12: Timer E Sub-Channel X Sub Capture/Compare Registers 0 To 2 (Cvsex0 To Cvsex2) (X = 1 To 4)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E sub-channel x sub capture/compare registers 0 to 2 (CVSEx0 to CVSEx2) (x = 1 to 4) The CVSExn register is a 16-bit sub channel x sub-capture/compare register of timer TMEn (x = 1 to 4) (n = 0 to 2).
Page 265: Figure 9-13: Timer E Sub-Channel 5 Capture/Compare Registers (Cvse50 To Cvse52)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E sub-channel 5 capture/compare registers 0 to 2 (CVSE50 to CVSE52) The CVSE5n register is the 16-bit sub-channel 5 capture/compare register of timer TMEn (n = 0 to In the capture register mode, it captures the count value of TBASE1n. In the compare register mode, it detects match with TBASE1n.
Page 266: Control Registers
Chapter 9 Timer / Counter (Real Time Pulse Unit) 9.2.4 Control Registers Timer E clock stop registers 0 to 2 (STOPTE0 to STOPTE2) The STOPTEn register is used to stop the operation clock input to timer TMEn (n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units.
Page 267: Figure 9-15: Timer E Count Clock/Control Edge Selection Registers 0 To 2 (Cse0 To Cse2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E count clock/control edge selection registers 0 to 2 (CSE0 to CSE2) The CSEn register is used to specify the timer TMEn count clock and the control valid edge (n = 0 to 2).
Page 268: Figure 9-16: Timer E Sub-Channel Input Event Edge Selection Register 0 To 2 (Sese0 To Sese2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E sub-channel input event edge selection registers 0 to 2 (SESE0 to SESE2) The SESEn register specifies the valid edge of the external capture signal input (TIExn) for the sub- channel x capture/compare register performing capture (x = 0 to 5, n = 0 to 2).
Page 269: Figure 9-17: Timer E Time Base Control Registers 0 To 2 (Tcre0 To Tcre2) (1/2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E time base control registers 0 to 2 (TCRE0 to TCRE2) The TCREn register controls the operation of timer TMEn (n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units. Figure 9-17: Timer E Time Base Control Registers 0 to 2 (TCRE0 to TCRE2) (1/2) Initial Address...
Page 270 Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-17: Timer E Time Base Control Registers 0 to 2 (TCRE0 to TCRE2) (2/2) Bit Position Bit Name Function 11, 3 ECEEy Specifies TBASEyn count operation enable/disable through ECLR signal input. 0: Don’t enable TBASEyn count operation 1: Enable TBASEyn count operation Cautions: 1.
Page 271: Figure 9-18: Timer E Output Control Registers 0 To 2 (Octle0 To Octle2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E output control registers 0 to 2 (OCTLE0 to OCTLE2) The OCTLEn register controls timer output from the TOExn pin (x = 1 to 4, n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units.
Page 272: Figure 9-19: Timer E Sub-Channel 0, 5 Capture/Compare Control Registers 0 To 2 (Cmse050 To Cmse052)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E sub-channel 0, 5 capture/compare control registers 0 to 2 (CMSE050 to CMSE052) The CMSE05n register controls timer TMEn sub-channel 0 capture/compare register (CVSE0n) and timer TMEn sub-channel 5 capture/compare register (CVSE5n) (n = 0 to 2). This register can be read/written in 16-bit units.
Page 273: Figure 9-20: Timer E Sub-Channel 1, 2 Capture/Compare Control Registers 0 To 2 (Cmse120 To Cmse122) (1/2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E sub-channel 1, 2 capture/compare control register 0 to 2 (CMSE120 to CMSE122) The CMSE12n register controls the timer TMEn sub-channel x sub capture/compare register (CVSExn) and the timer TMEn sub-channel x main capture/compare register (CVPExn) (x = 1, 2) (n = 0 to 2).
Page 274 Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-20: Timer E Sub-Channel 1, 2 Capture/Compare Control Registers 0 to 2 (CMSE120 to CMSE122) (2/2) Bit Position Bit Name Function 11, 3 LNKEx Selects capture event signal input from edge selection and specifies transfer opera- tion in compare register mode.
Page 275: Figure 9-21: Timer E Sub-Channel 3, 4 Capture/Compare Control Registers 0 To 2 (Cmse340 To Cmse342) (1/2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E sub-channel 3, 4 capture/compare control registers 0 to 2 (CMSE340 to CMSE342) The CMSE34n register controls the timer TMEn sub-channel x sub capture/compare register (CVSExn) and the timer TMEn sub-channel x main capture/compare register (CVPExn) (x = 3, 4) (n = 0 to 2).
Page 276 Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-21: Timer E Sub-Channel 3, 4 Capture/Compare Control Registers 0 to 2 (CMSE340 to CMSE342) (2/2) Bit Position Bit Name Function 11, 3 LNKEx Selects capture event signal input from edge selection and specifies transfer opera- tion in compare register mode.
Page 277: Figure 9-22: Timer E Time Base Status Register (Tbstate0 To Tbstate2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) Timer E time base status registers 0 to 2 (TBSTATE0 to TBSTATE2) The TBSTATEn register indicates the status of the time base counter TBASEyn (y = 0, 1) (n = 0 to This register can be read/written in 16-, 8-, or 1-bit units.
Page 278: Figure 9-23: Timer E Capture/Compare Status Registers 0 To 2 (Ccstate0 To Ccstate2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) (10) Timer E capture/compare status registers 0 to 2 (CCSTATE0 to CCSTATE2) The CCSTATEn register indicates the status of the timer TMEn sub-channel x sub capture/compare register (CVSExn) and the timer TMEn sub-channel x main capture/compare register (CVPExn) (x = 1 to 4) (n = 0 to 2).
Page 279: Figure 9-24: Timer E Output Delay Registers 0 To 2 (Odele0 To Odele2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) (11) Timer E output delay registers 0 to 2 (ODELE0 to ODELE2) The ODELEn register sets the output delay operation synchronized with the clock to the TOExn pin’s output delay circuit (x = 1 to 4) (n = 0 to 2). This register can be read/written in 16-, 8-, or 1-bit units.
Page 280: Figure 9-25: Timer E Software Event Capture Registers 0 To 2 (Csce0 To Csce2)
Chapter 9 Timer / Counter (Real Time Pulse Unit) (12) Timer E software event capture registers 0 to 2 (CSCE0 to CECE2) The CSCE0n register sets capture operation by software in the capture register mode (n = 0 to 2). This register can be read/written in 16-bit units.
Page 281: Operation
Chapter 9 Timer / Counter (Real Time Pulse Unit) 9.2.5 Operation Edge detection The edge detection timing is shown below. Figure 9-26: Edge Detection Timing Note TIEx, TCLREn, TCOUNTEy MUXTB0 ED1, ED2 ECLR Note: The set values of the TESyE1, TESyE0 bits and the CESE1, CESE0 bits of the CSEn register, and the IESEx1, IESEx0 bits of the SESEn register are shown.
Page 282: Figure 9-27: Timer E Up Count Timing
Chapter 9 Timer / Counter (Real Time Pulse Unit) Basic operation of timer E Figures 9-27 to 9-30 show the basic operation of timer E. Figure 9-27: Timer E Up Count Timing (When TCREn Register’s UDSEy1, UDSEy0 Bits = 00B, ECEEy Bit = 0, ECREy Bit = 0, CLREy Bit = 0, CASE1 Bit = 0) Note 1 OSTEy...
Page 283: Figure 9-28: External Control Timing Of Timer E
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-28: External Control Timing of Timer E (When TCREn Register’s UDSEy1, UDSEy0 Bits = 00B, OSTEy Bit = 0, CEEy Bit = 1, CASE1 Bit = 0) Note ECEEy Note ECREy Note CLREy...
Page 284: Figure 9-29: Operation In Timer E Up/Down Count Mode
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-29: Operation in Timer E Up/Down Count Mode (When TCREn Register’s ECEEy bit = 0, ECREy Bit = 0, CLREy Bit = 0, OSTEy Bit = 0, CEEy Bit = 1, CASE1 Bit = 0) Note 1 UDSEy1, UDSEy0 don't care...
Page 285: Figure 9-30: Timer E Timing In 32-Bit Cascade Operation Mode
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-30: Timer E Timing in 32-Bit Cascade Operation Mode (When TCREn Register’s UDSEy1, UDSEy0 Bits = 00B, ECEEy Bit = 0, ECREy Bit = 0, CLREy Bit = 0, OSTEy Bit = 0, CEEy Bit = 1, CASE1 Bit = 1) Note CASC CNT [TB0]...
Page 286: Figure 9-31: Block Diagram Of Timer E Multiplex Count Generation Circuit
Chapter 9 Timer / Counter (Real Time Pulse Unit) Operation of capture/compare register (sub-channels 1 to 4) Sub-channels 1 to 4 receive the count value of the timer TMEn multiplex count generation circuit (n = 0 to 2). The multiplex count generation circuit is an internal unit of the time base counters TBASE0n, TBASE1n that supplies the multiplex count value MUXCNT to sub-channels 1 to 4.
Page 287: Figure 9-32: Timer E Multiplex Count Timing
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-32: Timer E Multiplex Count Timing CNT (TB0) FFFEH FFFFH 0000H 0001H CNT (TB1) 1234H 1235H MUXTB0 MUXTB1 MUXCNT FFFEH 1234H FFFFH 1234H FFFFH 1234H FFFFH 1234H 0000H 1235H 0000H 1235H 0000H 1235H 0001H...
Page 288: Figure 9-33: Timer E Capture Operation: 16-Bit Buffer-Less Mode
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-33: Timer E Capture Operation: 16-Bit Buffer-Less Mode (When Operation Is Delayed Through Setting of LNKEx Bit of CMSEmn Register, and CMSEmn Register’s CCSEx Bit = 0, BFEEx Bit = 0, EEVEx Bit = 1, and CSCEn Register’s SEVEx Bit = 0) MUXTB0 MUXTB1...
Page 289: Figure 9-34: Timer E Capture Operation: Mode With 16-Bit Buffer
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-34: Timer E Capture Operation: Mode with 16-Bit Buffer Note 1 (When CMSEmn Register’s TB1Ex Bit = 0, TB0Ex Bit = 1, CCSEx Bit = 0, LNKEx Bit = 0, BFEEx Bit = 1, EEVEx Bit = 1, and CSCEn Register’s SEVEx Bit = 0) MUXTB0 MUXTB1...
Page 290: Figure 9-35: Timer E Capture Operation: 32-Bit Cascade Operation Mode
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-35: Timer E Capture Operation: 32-Bit Cascade Operation Mode (When CMSEmn Register’s TB1Ex Bit = 1, TB0Ex Bit = 1, CCSEx Bit = 0, LNKEx Bit = 0, BFEEx Bit = Arbitrary, EEVEx Bit = 1, and CSCEn Register’s SEVEx Bit = 0) TCOUNTE0 = TCOUNTE1 FFFEH...
Page 291: Figure 9-36: Timer E Capture Operation: Capture Control By Software And Trigger Timing
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-36: Timer E Capture Operation: Capture Control by Software and Trigger Timing (When CMSEmn Register’s TB1Ex Bit = 0, TB0Ex Bit = 1, CCSEx Bit = 0, LNKEx Bit = 0, BFEEx Bit = 1) MUXTB0 MUXTB1...
Page 292: Figure 9-37: Timer E Compare Operation: Buffer-Less Mode
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-37: Timer E Compare Operation: Buffer-Less Mode (When CMSEmn Register’s CCSEx Bit = 1, LNKEx Bit = Arbitrary, BFEEx Bit = 0) MUXTB0 MUXTB1 MUXCNT Note 1 TB0Ex Note 1 TB1Ex WRITE_ENABLE_S RELOAD_PRIMARY...
Page 293: Figure 9-38: Timer E Compare Operation: Mode With Buffer
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-38: Timer E Compare Operation: Mode with Buffer (When CMSEmn Register’s CCSEx Bit = 1, BFEEx Bit = 1, and Operation Is Delayed Through Setting of LNKEx Bit) MUXTB0 MUXTB1 MUXCNT Note LNKEx...
Page 294: Figure 9-39: Timer E Capture Operation: Count Value Read Timing
Chapter 9 Timer / Counter (Real Time Pulse Unit) Operation of capture/compare register (sub-channels 0, 5) Figures 9-39 and 9-40 show the operation of the capture/compare register (sub-channels 0, 5). Figure 9-39: Timer E Capture Operation: Count Value Read Timing (When CMSE05n Register’s CCSEx Bit = 0, EEVEx Bit = 1, and CSCEn Register’s SEVEx Bit = 0) Note 1...
Page 295: Figure 9-40: Timer E Compare Operation: Timing Of Compare Match And Write Operation To Register
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-40: Timer E Compare Operation: Timing of Compare Match and Write Operation to Register (When CMSE05n Register’s CCSEx Bit = 1, EEVEx Bit = Arbitrary, and CSCE0n Register’s SEVEx Bit = Arbitrary) CPU write C/C CVSExn register MATCH...
Page 296: Figure 9-41: Timer E Signal Output Operation: Toggle Mode 0 And Toggle Mode 1
Chapter 9 Timer / Counter (Real Time Pulse Unit) Operation of output circuit Figures 9-41 to 9-44 show the output circuit operation. Figure 9-41: Timer E Signal Output Operation: Toggle Mode 0 and Toggle Mode 1 (When OCTLEn Register’s SWFEx Bit = 0, and ODELEn Register’s ODLEx2 to ODLEx0 Bits = 0) Note OTMEx1, OTMEx0...
Page 297: Figure 9-42: Timer E Signal Output Operation: Toggle Mode 2 And Toggle Mode 3
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-42: Timer E Signal Output Operation: Toggle Mode 2 and Toggle Mode 3 (When OCTLEn Register’s SWFEx Bit = 0, and ODELEn Register’s ODLEx2 to ODLEx0 Bits = 0) Note OTMEx1, OTMEx0 bits TOExn timer output Note...
Page 298: Figure 9-43: Timer E Signal Output Operation: During Software Control
Chapter 9 Timer / Counter (Real Time Pulse Unit) Figure 9-43: Timer E Signal Output Operation: During Software Control (When OCTLEn Register’s OTMEx1, OTMEx0 Bits = Arbitrary, SWFEx Bit = 1, and ODELEn Register’s ODLEx2 to ODLEx0 Bits = 0) Note ALVEx TOExn timer output...
Page 299: Chapter 10 Watch Timer
Chapter 10 Watch Timer 10.1 Function The watch timer has the following functions: • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. Figure 10-1 shows the block diagram of the watch timer. Figure 10-1: Block Diagram of Watch Timer Clear 5-bit counter...
Page 300: Configuration
Chapter 10 Watch Timer Watch timer The watch timer generates an interrupt request (INTWT) at time intervals of 512 µs or 2.097 s by using the subsystem clock f or f or the derived 11-bit prescaler clock from f CKSEL1 CKSEL2 CKSEL1 (refer to Figure 8-1: “Block Diagram of the Clock Generator”...
Page 301: Watch Timer Control Register
Chapter 10 Watch Timer 10.3 Watch Timer Control Register The watch timer mode control register (WTM) controls the watch timer. Watch timer mode control register (WTM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 302 Chapter 10 Watch Timer Sub Clock f Input Clock 4 MHz 31250 Hz CKSEL1 4 MHz 7812.5 Hz CKSEL2 5 MHz 39062.5 Hz CKSEL1 5 MHz 9765.625 Hz CKSEL2 Preliminary User’s Manual U14913EE1V0UM00...
Page 303: Operations
Chapter 10 Watch Timer 10.4 Operations 10.4.1 Operation as watch timer Note The watch timer operates with time intervals from 2.09715 s to 512 µs with fw of 31250 Hz / 7812.5 Hz. The watch timer generates an interrupt request at fixed time intervals. The count operation of the watch timer is started when bits 0 (WTM0) and 1 (WTM1) of the watch timer mode control register (WTM) are set to 1.
Page 304: Figure 10-3: Operation Timing Of Watch Timer/Interval Timer
Chapter 10 Watch Timer Figure 10-3: Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock f Watch timer interrupt INTWT Note Note Interrupt time of watch timer Interrupt time of watch timer Interval timer interrupt INTWTI Interval time (T) Interval time (T) Notes:...
Page 305: Chapter 11 Watchdog Timer
Chapter 11 Watchdog Timer • Features: - Generates reset or NMI (selectable) - Have to be started once by software control (afterwards protected) - Will operate at system frequency divided by 4 to get a lower watch limit of 1ms. Figure 11-1: Block Diagram of Watchdog Timer Unit CKSEL1 Watchdog Timer...
Page 306: Control Register
Chapter 11 Watchdog Timer 11.2 Control Register 11.2.1 Watchdog timer mode register (WDTM) This register sets the operating mode of the watchdog timer, and enables and disables counting. This register sets the overflow times of the watchdog timer. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H.
Page 307: Operation
Chapter 11 Watchdog Timer 11.3 Operation 11.3.1 Operating as watchdog timer Set bit 6 (WDTM) of the watchdog timer mode register (WDTM) to 1 to operate as a watchdog timer to detect program runaway and generate an RESET signal. Setting bit 7 (WDTEN) of WDTM to 1 starts the count. After counting starts, if WDTEN is set to 1 again within the set time interval for runaway detection, the watchdog timer is cleared and counting starts again.
Page 308 [MEMO] Preliminary User’s Manual U14913EE1V0UM00...
Page 309: Chapter 12 Serial Interface Function
Chapter 12 Serial Interface Function 12.1 Features The serial interface function provides three types of serial interfaces combining a total of eight transmit/ receive channels. All channels can be used simultaneously. The three interface formats are as follows. (1) Asynchronous serial interfaces (UART0 to UART2): 3 channels (2) Clocked serial interfaces (CSI0, CSI1): 2 channels (3) FCAN controller: 3 channels Remark: For details about the FCAN controller, refer to Chapter 13...
Page 310: Asynchronous Serial Interfaces 0 To 2 (Uart0, Uart1, Uart2)
Chapter 12 Serial Interface Function 12.2 Asynchronous Serial Interfaces 0 to 2 (UART0, UART1, UART2) 12.2.1 Features • Transfer rate: 300 bps to 625 Kbps (using a dedicated baud rate generator and an internal system clock of 20 MHz) • Full-duplex communications - On-chip reception buffer register (RXBn) - On-chip transmission buffer register (TXBn)
Page 311: Configuration
Chapter 12 Serial Interface Function 12.2.2 Configuration UARTn is controlled by the asynchronous serial interface mode register (ASIMn), asynchronous serial interface status register (ASISn), and asynchronous serial interface transmission status register (ASIFn). Receive data is maintained in the reception buffer register (RXBn), and transmit data is written to the transmission buffer register (TXBn).
Page 312: Figure 12-1: Asynchronous Serial Interfaces 0 To 2 Block Diagram
Chapter 12 Serial Interface Function Transmission buffer registers 0 to 2 (TXB0 to TXB2) TXBn is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXBn. The transmission completion interrupt request (INTSTn) is generated synchronized with the completion of transmission of one frame.
Page 313: Control Registers
Chapter 12 Serial Interface Function 12.2.3 Control registers Asynchronous serial interface mode registers 0 to 2 (ASIM0 to ASIM2) The ASIMn register is an 8-bit register that controls the UARTn transfer operation. This register can be read/written in 8 bit or 1-bit units (n = 0 to 2). Figure 12-2: Asynchronous Serial Interface Mode Registers 0 to 2 (ASIM0 to ASIM2) (1/3) Address Initial...
Page 314 Chapter 12 Serial Interface Function Figure 12-2: Asynchronous Serial Interface Mode Registers 0 to 2 (ASIM0 to ASIM2) (2/3) Bit Position Bit Name Function Enables/disables reception. 0: Disable reception (Perform synchronous reset of reception circuit) 1: Enable reception Cautions: 1. Set the RXE bit to 1 after setting the CAE bit to 1 when starting transfer.
Page 315 Chapter 12 Serial Interface Function Figure 12-2: Asynchronous Serial Interface Mode Registers 0 to 2 (ASIM0 to ASIM2) (3/3) Bit Position Bit Name Function 4, 3 PS1, PS0 • 0 parity During transmission, the parity bit is cleared (0) regardless of the transmit data.
Page 316: Figure 12-3: Asynchronous Serial Interface Status Registers 0 To 2 (Asis0 To Asis2)
Chapter 12 Serial Interface Function Asynchronous serial interface status registers 0 to 2 (ASIS0 to ASIS2) The ASISn register, which consists of 3-bit error flags (PE, FE and OVE), indicates the error status when UARTn reception is completed. The status flag, which indicates a reception error, always indicates the status of the error that occurred most recently.
Page 317: Figure 12-4: Asynchronous Serial Interface Transmit Status Registers 0 To 2 (Asif0 To Asif2)
Chapter 12 Serial Interface Function Asynchronous serial interface transmission status registers 0 to 2 (ASIF0 to ASIF2) The ASIFn register, which consists of 2-bit status flags, indicates the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmission shift register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 318: Figure 12-5: Reception Buffer Registers 0 To 2 (Rxb0 To Rxb2)
Chapter 12 Serial Interface Function Reception buffer registers 0 to 2 (RXB0 to RXB2) The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the reception shift register. When reception is enabled (RXE bit = 1 in the ASIMn register), receive data is transferred from the reception shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame.
Page 319: Figure 12-6: Transmission Buffer Registers 0 To 2 (Txb0 To Txb2)
Chapter 12 Serial Interface Function Transmission buffer registers 0 to 2 (TXB0 to TXB2) The TXBn register is an 8-bit buffer register for setting transmit data. When transmission is enabled (TXE bit = 1 in the ASIMn register), the transmit operation is started by writing data to TXBn register.
Page 320: Interrupt Requests
Chapter 12 Serial Interface Function 12.2.4 Interrupt requests The following three types of interrupt requests are generated from UART0 to UART2. • Reception error interrupt (INTSERn) • Reception completion interrupt (INTSRn) • Transmission completion interrupt (INTSTn) The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt (n = 0 to 2).
Page 321: Operation
Chapter 12 Serial Interface Function 12.2.5 Operation Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 12-7. The character bit length within one data frame, the type of parity, and the stop bit length are speci- fied according to the asynchronous serial interface mode register (ASIMn) (n = 0 to 2).
Page 322: Figure 12-8: Asynchronous Serial Interface Transmission Completion Interrupt Timing
Chapter 12 Serial Interface Function Transmit operation When CAE bit is set to 1 in the ASIMn register, a high level is output from the TXDn pin. Then, when TXE bit is set to 1 in the ASIMn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmission buffer register (TXBn) (n = 0 to 2).
Page 323: Table 12-2: Transmission Status And Whether Or Not Writing Is Enabled
Chapter 12 Serial Interface Function Continuous transmission operation UARTn can write the next transmit data to the TXBn register at the time that the transmission shift register starts the shift operation. This enables an efficient transmission rate to be realized by con- tinuously transmitting data even during the INTSTn interrupt service after the transmission of one data frame.
Page 324: Figure 12-9: Continuous Transmission Starting Procedure
Chapter 12 Serial Interface Function (a) Starting procedure Figure 12-9 shows the procedure to start continuous transmission. Figure 12-9: Continuous Transmission Starting Procedure TXDn Start Data (1) Parity Stop Start Data (2) Parity Stop (output) INTSTn (output) TXBn Data (1) Data (2) Data (3) register...
Page 325: Figure 12-10: Continuous Transmission End Procedure
Chapter 12 Serial Interface Function (b) Ending procedure Figure 12-10: Continuous Transmission End Procedure TXDn Data Data (n − 1) Parity Start Parity Start Parity Stop Stop Data (n) Stop (n − 2) (output) INTSTn (output) TXBn Data (n − 1) Data (n) register Transmission...
Page 326: Figure 12-11: Asynchronous Serial Interface Reception Completion Interrupt Timing
Chapter 12 Serial Interface Function Receive operation An awaiting reception state is set by setting CAE bit to 1 in the ASIMn register and then setting RXE bit to 1 in the ASIMn register. To start a receive operation, detects a start bit first. The start bit is detected by sampling RXDn pin.
Page 327: Figure 12-12: When Reception Error Interrupt Is Separated From Intsrn Interrupt (Isrm Bit = 0)
Chapter 12 Serial Interface Function Reception error The three types of error that can occur during a receive operation are a parity error, framing error, or overrun error. The data reception result is that the various flags of the ASISn register are set (1), and a reception error interrupt (INTSERn) or a reception completion interrupt (INTSRn) is gener- ated at the same time.
Page 328 Chapter 12 Serial Interface Function Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (a) Even parity -During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 329: Figure 12-14: Noise Filter Circuit
Chapter 12 Serial Interface Function Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output basic clock (Clock). If the same sampling value is obtained twice, the match detector output changes, and this output is sam- pled as input data.
Page 330: Dedicated Baud Rate Generators (Brg) Of Uartn (N = 0 To 2)
Chapter 12 Serial Interface Function 12.2.6 Dedicated baud rate generators (BRG) of UARTn (n = 0 to 2) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception at UARTn (n = 0 to 2). The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 331: Figure 12-17: Clock Select Registers 1 To 3 (Cksr1 To Cksr3)
Chapter 12 Serial Interface Function Serial clock generation A serial clock can be generated according to the settings of the CKSRm and BRGCm registers. The basic clock to the 8-bit counter is selected according to the TPS3 to TPS0 bits of the CKSRm register.
Page 332: Figure 12-18: Baud Rate Generator Control Registers 0 To 2 (Brgc0 To Brgc2)
Chapter 12 Serial Interface Function (b) Baud rate generator control registers 0 to 2 (BRGC0 to BRGC2) The BRGCm register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. This register can be read or written in 8-bit or 1-bit units (m = 0 to 2). Figure 12-18: Baud Rate Generator Control Registers 0 to 2 (BRGC0 to BRGC2) Address Initial...
Page 333 Chapter 12 Serial Interface Function (c) Baud rate The baud rate is the value obtained according to the following formula. ----------- Baud rate 2 k ⋅ = Frequency [Hz] of basic clock selected according to TPS3 to TPS0 bits of CKSRm register.
Page 334: Table 12-4: Baud Rate Generator Setting Data
Chapter 12 Serial Interface Function (e) Baud rate setting example Table 12-4: Baud Rate Generator Setting Data = 20 MHz = 16 MHz = 5 MHz = 4 MHz Baud Rate [bps] /256 /256 0.16 0.16 0.16 0.16 /128 /128 0.16 0.16 0.16...
Page 335: Figure 12-19: Allowable Baud Rate Range During Reception
Chapter 12 Serial Interface Function Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution: The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 336: Table 12-5: Maximum And Minimum Allowable Baud Rate Error
Chapter 12 Serial Interface Function Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. 21k 2 – × × × × ----- - ------------ ------------------ - FLmax 11 FL – 21k 2 – × × FLmax ------------------ - Therefore, the transfer destination’s minimum baud rate (BRmin) that can be received is as follows.
Page 337: Precautions
Chapter 12 Serial Interface Function Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of basic clock (Clock) longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 338: Clocked Serial Interfaces 0, 1 (Csi0, Csi1)
Chapter 12 Serial Interface Function 12.3 Clocked Serial Interfaces 0, 1 (CSI0, CSI1) 12.3.1 Features • High-speed transfer: Maximum 5 Mbps • Master mode or slave mode can be selected • Transmission data length: 8 bits or 16 bits • Transfer data direction can be switched between MSB first and LSB first •...
Page 339: Configuration
Chapter 12 Serial Interface Function 12.3.2 Configuration CSIn is controlled via the clocked serial interface mode register (CSIMn) (n = 0, 1). Transmission/reception of data is performed with reading SIOn register (n = 0, 1). Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register is an 8-bit register that specifies the operation of CSIn.
Page 340: Figure 12-21: Block Diagram Of Clocked Serial Interfaces
Chapter 12 Serial Interface Function (12) Clocked serial interface initial transmission buffer registers L0, L1 (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmit data in the repeat transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock control circuit Controls the serial clock supply to the shift register.
Page 341: Control Registers
Chapter 12 Serial Interface Function 12.3.3 Control registers Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register controls the CSIn operation (n = 0, 1). These registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). Figure 12-22: Clocked Serial Interface Mode Registers 0, 1 (CSIM0, CSIM1) Address Initial...
Page 342: Figure 12-23: Clocked Serial Interface Clock Selection Registers 0, 1 (Csic0, Csic1)
Chapter 12 Serial Interface Function Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1) The CSICn register is an 8-bit register that controls the CSIn transfer operation (n = 0, 1). This register can be read/written in 8-bit or 1-bit units. Figure 12-23: Clocked Serial Interface Clock Selection Registers 0, 1 (CSIC0, CSIC1) Address Initial...
Page 343: Figure 12-24: Clocked Serial Interface Reception Buffer Registers 0, 1 (Sirb0, Sirb1)
Chapter 12 Serial Interface Function Clocked serial interface reception buffer registers 0, 1 (SIRB0, SIRB1) The SIRBn register is a 16-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMD bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBn register.
Page 344: Figure 12-25: Clocked Serial Interface Reception Buffer Registers L0, L1 (Sirbl0, Sirbl1)
Chapter 12 Serial Interface Function Clocked serial interface reception buffer registers L0, L1 (SIRBL0, SIRBL1) The SIRBLn register is an 8-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMD bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBLn register.
Page 345: Figure 12-26: Clocked Serial Interface Read-Only Reception Buffer Registers 0, 1 (Sirbe0, Sirbe1)
Chapter 12 Serial Interface Function Clocked serial interface read-only reception buffer registers 0, 1 (SIRBE0, SIRBE1) The SIRBEn register is a 16-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIE bit of the CSIMn register.
Page 346: Figure 12-27: Clocked Serial Interface Read-Only Reception Buffer Registers L0, L1(Sirbel0, Sirbel1)
Chapter 12 Serial Interface Function Clocked serial interface read-only reception buffer registers L0, L1 (SIRBEL0, SIRBEL1) The SIRBELn register is an 8-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 8-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIE bit of the CSIMn register.
Page 347: Figure 12-28: Clocked Serial Interface Transmission Buffer Registers 0, 1 (Sotb0, Sotb1)
Chapter 12 Serial Interface Function Clocked serial interface transmission buffer registers 0, 1 (SOTB0, SOTB1) The SOTBn register is a 16-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMD bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBn register.
Page 348: Figure 12-29: Clocked Serial Interface Transmission Buffer Registers L0, L1 (Sotbl0, Sotbl1)
Chapter 12 Serial Interface Function Clocked serial interface transmission buffer registers L0, L1 (SOTBL0, SOTBL1) The SOTBLn register is an 8-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMD bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBLn register.
Page 349: Figure 12-30: Clocked Serial Interface Initial Transmission Buffer Registers 0, 1 (Sotbf0, Sotbf1)
Chapter 12 Serial Interface Function Clocked serial interface initial transmission buffer registers 0, 1 (SOTBF0, SOTBF1) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFn register. These registers can be read/written in 16-bit units.
Page 350: Figure 12-31: Clocked Serial Interface Initial Transmission Buffer Registers L0, L1 (Sotbfl0, Sotbfl1)
Chapter 12 Serial Interface Function (10) Clocked serial interface initial transmission buffer registers L0, L1 (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFLn register. These registers can be read/written in 8-bit units.
Page 351: Figure 12-32: Serial I/O Shift Registers 0, 1 (Sio0, Sio1)
Chapter 12 Serial Interface Function (11) Serial I/O shift registers 0, 1 (SIO0, SIO1) The SIOn register is a 16-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOn register is read. These registers are read-only, in 16-bit units.
Page 352: Figure 12-33: Serial I/O Shift Registers L0, L1 (Siol0, Siol1)
Chapter 12 Serial Interface Function (12) Serial I/O shift registers L0, L1 (SIOL0, SIOL1) The SIOLn register is an 8-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOLn register is read. These registers are read-only, in 8-bit units.
Page 353: Operation
Chapter 12 Serial Interface Function 12.3.4 Operation Single transfer mode (a) Usage Note 1 In the receive-only mode (TRMD bit of CSIMn register = 0), transfer is started by reading receive data buffer register (SIRBn/SIRBLn) (n = 0, 1). In the transmission/reception mode (TRMD bit of CSIMn register = 1), transfer is started by Note 2 writing to the transmit data buffer register (SOTBn/SOTBLn).
Page 354 Chapter 12 Serial Interface Function Figure 12-34: Timing Chart in Single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 1 SCKn (input/output) (55H)
Page 355: Figure 12-35: Timing Chart According To Clock Phase Selection (1/2)
Chapter 12 Serial Interface Function (b) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKP bit of CSICn register) and data phase selection (DAP bit of CSICn register) under the following condi- tions.
Page 356 Chapter 12 Serial Interface Function Figure 12-35: Timing Chart According to Clock Phase Selection (2/2) (c) When CKP bit = 0, DAP bit = 1 SCKn (input/output) SIn (input) DO6 DO5 DO4 DO3 DO2 DO1 SOn (output) Reg_R/W INTCSIn interrupt CSOT bit (d) When CKP bit = 1, DAP bit = 1 SCKn (input/output)
Page 357: Figure 12-36: Timing Chart Of Interrupt Request Signal Output In Delay Mode (1/2)
Chapter 12 Serial Interface Function (c) Transmission/reception completion interrupt request signals (INTCSI0, INTCSI1) INTCSI0n is set (1) upon completion of data transmission/reception. Caution: The delay mode (CSIT bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of the CSICn register are not 111B).
Page 358 Chapter 12 Serial Interface Function Figure 12-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2) (b) When CKP bit = 1, DAP bit = 1 Input clock SCKn (input/output) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOT bit Delay Remarks: 1.
Page 359: Figure 12-37: Repeat Transfer (Receive-Only) Timing Chart
Chapter 12 Serial Interface Function Repeat transfer mode (a) Usage (receive-only) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the receive-only mode (TRMD bit of CSIMn register = 0). <2> Read SIRBn register (start transfer with dummy read). <3>...
Page 360: Figure 12-38: Repeat Transfer (Transmission/Reception) Timing Chart
Chapter 12 Serial Interface Function (b) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the transmission/reception mode (TRMD bit of CSIMn register = 1). <2> Write the first data to the SOTBFn register. <3>...
Page 361: Figure 12-39: Timing Chart Of Next Transfer Reservation Period
Chapter 12 Serial Interface Function (c) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared with the period shown in Figure 12- Figure 12-39: Timing Chart of Next Transfer Reservation Period (a) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 0 SCKn (input/output) INTCSIn...
Page 362: Figure 12-40: Transfer Request Clear And Register Access Contention
Chapter 12 Serial Interface Function (d) Cautions To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs.
Page 363: Figure 12-41: Interrupt Request And Register Access Contention
Chapter 12 Serial Interface Function - In case of contention between interrupt request and register access Since continuous transfer has stopped once, executed as a new repeat transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 12-41). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent.
Page 364: Output Pins
Chapter 12 Serial Interface Function 12.3.5 Output pins SCKn pin When the CSIn operation is disabled (CSIE bit of CSIMn register = 0), the SCKn pin output status is as follows (n = 0, 1). CKS2 CKS1 CKS0 SCKn Pin Output Don’t care Don’t care Don’t care...
Page 365: Dedicated Baud Rate Generators 0, 1 (Brg0, Brg1)
Chapter 12 Serial Interface Function 12.3.6 Dedicated baud rate generators 0, 1 (BRG0, BRG1) Selecting the baud rate generator The CSI0 and CSI1 serial clocks can be selected between dedicated baud rate generator output or internal system clock ( The serial clock source is specified by bits CKS2 to CKS0 of registers CSIC0 and CSIC1 (refer to 12.3.3 (2)Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1)).
Page 366: Figure 12-43: Prescaler Mode Registers 0, 1 (Prsm0, Prsm1)
Chapter 12 Serial Interface Function Configuration BRGn is configured of an 8-bit timer counter that generates the baud rate signal, a prescaler mode register n (PRSMn) that controls baud rate signal generation, a prescaler compare register n (PRSCMn) that sets the value of the 8-bit timer counter, and a prescaler (n = 0, 1). (a) Input clock The internal system clock (f ) is input to BRGn.
Page 367: Figure 12-44: Prescaler Compare Registers 0, 1 (Prscm0, Prscm1)
Chapter 12 Serial Interface Function (c) Prescaler compare registers 0, 1 (PRSCM0, PRSCM1) PRSCMn is an 8-bit compare register that sets the value of the 8-bit timer counter. This register can be read/written in 8-bit or 1-bit units (n = 0, 1). Figure 12-44: Prescaler Compare Registers 0, 1 (PRSCM0, PRSCM1) Address Initial...
Page 368: Table 12-6: Baud Rate Generator Setting Data
Chapter 12 Serial Interface Function (e) Baud rate setting example Table 12-6: Baud Rate Generator Setting Data <1> When f = 16 MHz BGCS1 BGCS0 PRSCM Register Value Clock (Hz) 4000000 2000000 1000000 500000 250000 100000 50000 25000 10000 5000 <2>...
Page 369: Chapter 13 Fcan Interface Function
Chapter 13 FCAN Interface Function 13.1 Features • Active support of extended format (ISO 11898, former CAN specification version 2.0B active), sup- porting transmission and reception of standard and extended frame format messages • 3 CAN modules • CAN bus speed up to 1 Mbit per second •...
Page 370: Outline Of The Fcan System
Chapter 13 FCAN Interface Function 13.2 Outline of the FCAN System 13.2.1 General The FCAN (Full-CAN) system of the V850E/CA1 (Atomic) supports 3 independent CAN modules (CAN module 1, CAN module 2, CAN module 3), which provide each an interface to a Controller Area Net- work (CAN).
Page 371: Can Memory And Register Layout
Chapter 13 FCAN Interface Function 13.2.2 CAN memory and register layout All buffers and registers of the FCAN system are arranged within a memory layout of 3 KB. Figure 13-2: Memory Area of the FCAN System Address Offset 8FFH CAN3 temporary buffer 8E0H 8DFH CAN3 register section...
Page 372: Table 13-1: Configuration Of The Can Message Buffer Section
Chapter 13 FCAN Interface Function CAN message buffer section The message buffer section consists of 64 message buffers. Each message buffer allocates 32 bytes. The message buffers are not statically distributed and linked to the CAN modules, rather the user must determine the link of a message buffer to a CAN module by software.
Page 373: Table 13-2: Can Message Buffer Registers Layout
Chapter 13 FCAN Interface Function Table 13-2: CAN Message Buffer Registers Layout Access Type Ref. Address Offset Note 1 Name Symbol Page Note 1, 2 1 bit 8 bit 16 bits (m × 20H) + 000H × M_EVTm0 Message event register 0 (m ×...
Page 374: Table 13-3: Relative Addresses Of Can Interrupt Pending Registers
Chapter 13 FCAN Interface Function CAN Interrupt Pending Registers Section The layout of the interrupt pending register section is shown in Table 13-3. Table 13-3: Relative Addresses of CAN Interrupt Pending Registers Access Type Address Off- Ref. Symbol Name Comment Note Page R/W 1 bit 8 bits 16 bits...
Page 375: Table 13-4: Relative Addresses Of Can Common Registers
Chapter 13 FCAN Interface Function CAN Common Registers Section The layout of the common register section is shown in Table 13-4. Table 13-4: Relative Addresses of CAN Common Registers Access Type Address Ref. Symbol Name Comment Note Page Offset R/W 1 bit 8 bits 16 bits ×...
Page 376: Table 13-5: Relative Addresses Of Can Module 1 Registers
Chapter 13 FCAN Interface Function CAN Module Registers Section The appropriate register section of each CAN module is shown in Table 13-5 for CAN module 1, in Table 13-6 for CAN module 2 and in Table 13-7 for CAN module 3. Table 13-5: Relative Addresses of CAN Module 1 Registers Access Type Address...
Page 377: Table 13-6: Relative Addresses Of Can Module 2 Registers
Chapter 13 FCAN Interface Function Table 13-6: Relative Addresses of CAN Module 2 Registers Access Type Address Ref. Symbol Name Comment Note Page Offset R/W 1 bit 8 bits 16 bits × × 880H C2MASKL0 CAN2 mask 0 register L lower half-word ×...
Page 378: Table 13-7: Relative Addresses Of Can Module 3 Registers
Chapter 13 FCAN Interface Function Table 13-7: Relative Addresses of CAN Module 3 Registers Access Type Address Ref. Symbol Name Comment Note Page Offset R/W 1 bit 8 bits 16 bits × × 8C0H C3MASKL0 CAN3 mask 0 register L lower half-word ×...
Page 379: Table 13-8: Relative Addresses Of Can Bridge Elisa Registers
Chapter 13 FCAN Interface Function CAN Bridge ELISA Register Section The layout of the ELISA register section is shown in Table 13-8. Table 13-8: Relative Addresses of CAN Bridge ELISA Registers Access Type Address Ref. Symbol Name Comment Note Page Offset R/W 1 bit 8 bits 16 bits ×...
Page 380: Clock Structure
Chapter 13 FCAN Interface Function 13.2.3 Clock structure All functional blocks within the FCAN system are supplied by a unique clock (f ) derived from the internal system clock (f ) or an external clock (f Figure 13-3: Clock Structure of the FCAN System Time System General Time System...
Page 381: Interrupt Handling
Chapter 13 FCAN Interface Function 13.2.4 Interrupt handling The very high number of interrupt events generated by the FCAN system does not allow to assign an independent interrupt vector of the V850E/CA1 (Atomic) to each event. Therefore, the interrupt request signals are bundled into groups and the grouped interrupt request signal is then assigned to an inde- pendent interrupt vector.
Page 382: Time Stamp
Chapter 13 FCAN Interface Function 13.2.5 Time stamp The FCAN system offers a time stamp capture capability at message reception and transmission. The time stamp capture function is used to realize a synchronized, global clock in a CAN network, also called global time system.
Page 383: Figure 13-6: Time Stamp Capturing At Message Transmission
Chapter 13 FCAN Interface Function For the time stamp capturing at message transmission the SOF signal of the transmit message is used as the event trigger (see Figure 13-6). The captured value from the CGTSC counter is written into particular data bytes of the transmit mes- sage’s data field.
Page 384: Message Handling
Chapter 13 FCAN Interface Function 13.2.6 Message handling In the FCAN system the assignment of message buffers to the CAN modules is not defined by hard- ware. Each message buffer in the message buffer section can be assigned to any CAN module by soft- ware.
Page 385: Table 13-10: Example For Automatic Transmission Priority Detection
Chapter 13 FCAN Interface Function Table 13-10: Example for Automatic Transmission Priority Detection Message Buffer Message Buffer Message Buffer Message Buffer Waiting for Identifier Note1 Number Link Note2 Transmission Address Offset Type 7E0H · · · · · · 300H 2E0H 2C0H CAN 1...
Page 386: Table 13-11: Example For Transmit Buffer Allocation When More Than 5 Buffers Linked To A Can Module
Chapter 13 FCAN Interface Function Table 13-11: Example for Transmit Buffer Allocation When More Than 5 Buffers Linked to a CAN Module Message Buffer Message Buffer Message Buffer Message Buffer Identifier Note1 Number Link Note2 Address Offset Type 7E0H · ·...
Page 387: Table 13-12: Storage Priority For Reception Of Data Frames
Chapter 13 FCAN Interface Function Message reception Due to the vast initialisation possibilities for each message buffer in the FCAN system, it is possible that a received message fits in several message buffers assigned to a CAN module. A fixed rule according to the priority classes has been implemented to avoid arbitrary message stor- age and uncontrolled behaviour.
Page 388: Table 13-14: Inner Storage Priority Within A Priority Class
Chapter 13 FCAN Interface Function Table 13-14: Inner Storage Priority Within a Priority Class Priority First Criteria Priority Second Criteria 1 (high) lowest physical message buffer number 1 (high) DN flag not set 2 (low) next physical message buffer number 1 (high) lowest physical message buffer number 2 (low)
Page 389: Mask Handling
Chapter 13 FCAN Interface Function 13.2.7 Mask handling The FCAN system supports two concepts of message reception, the BasicCAN concept and the Full- CAN concept. In the Full-CAN concept a particular message buffer accepts only one single message, hence there is no further sorting and filtering required by software.
Page 390: Remote Frame Handling
Chapter 13 FCAN Interface Function 13.2.8 Remote frame handling The FCAN macro offers enhanced features for generating remote frames and for the reaction of a CAN module upon remote frames. Generation of a remote frame According to the CAN specification a remote frame has the same format as a data frame except the RTR bit of the control field, which has recessive level, and the data field, which is omitted com- pletely.
Page 391 Chapter 13 FCAN Interface Function Reception of a remote frame The FCAN allows the reception of remote frames in message buffers defined for reception or for transmission. (a) Reception in a receive message buffer If a remote frame is received in a message buffer m (m = 00 to 63) configured for reception, the fol- lowing message buffer information will be updated: M_DLCm message data length code register...
Page 392: Table 13-15: Remote Frame Handling Upon Reception Into A Transmit Message Buffer
Chapter 13 FCAN Interface Function (b) Reception in a transmit message buffer When the FCAN system searches for the corresponding message buffer after reception of a remote frame and finds a message buffer with a matching identifier, which is defined for transmission, the content of the remote frame is not stored but programmable reactions are launched.
Page 393: Fcan System Event Handling
Chapter 13 FCAN Interface Function 13.2.9 FCAN System Event Handling The modular designed FCAN system allows the connection not only of CAN modules to the mes- sage buffers, but also of other machines assigned to do (for example) data or time management. The requirements of a modular concept allowing several CAN modules and other machines to be operated on the same “system”...
Page 394: Control And Data Registers
Chapter 13 FCAN Interface Function 13.3 Control and Data Registers 13.3.1 Bit set/clear function Direct writing of data (bit operations, read-modify write, direct writing of a target value) is not allowed to few specific registers, where bit setting and bit clearing might be performed by CPU and by the FCAN system.
Page 395: Figure 13-7: 16-Bit Data Write Operation For Specific Registers
Chapter 13 FCAN Interface Function Figure 13-7: 16-Bit Data Write Operation for Specific Registers ST_7 ST_6 ST_5 ST_4 ST_3 ST_2 ST_1 ST_0 CL_7 CL_6 CL_5 CL_4 CL_3 CL_2 CL_1 CL_0 Bit Name Function ST_n Sets the register bit n. 0: No change of register bit n 1: Register bit n is set (1) CL_n Clears the register bit n.
Page 396: Common Registers
Chapter 13 FCAN Interface Function 13.3.2 Common registers CAN stop register (CSTOP) The CSTOP register controls the clock supply of the FCAN system. This register can be read/written in 8-bit and16-bit units. Figure 13-8: CAN Stop Register (CSTOP) Address Initial Note Offset value...
Page 397: Figure 13-9: Can Main Clock Select Register (Cgsc) (1/2)
Chapter 13 FCAN Interface Function CAN main clock select register (CGCS) The CGCS register controls the internal memory access clock (f ), which is used as main clock for each CAN module, as well as the global time system clock (f ), used for the time stamp func- tion and event generation.
Page 398: Figure 13-10: Configuration Of Fcan System Main Clock
Chapter 13 FCAN Interface Function Figure 13-9: CAN Main Clock Select Register (CGSC) (2/2) Bit Position Bit Name Function 3 to 0 MCP3 to Specifies the prescaler for the memory access clock (f ) (ref. to Fig. 13-10). MCP0 Memory Clock Prescaler MCP3 MCP2...
Page 399: Figure 13-12: Can Global Status Register (Cgst) (1/2)
Chapter 13 FCAN Interface Function CAN global status register (CGST) The CGST register indicates and controls the operation modes of the FCAN system. Additionally the version number of the FCAN system can be obtained. This register can be read in 1-bit, 8-bit and 16-bit units. It can be written in 16-bit units only. For set- ting and clearing certain bits a special set/clear method applies.
Page 400 Chapter 13 FCAN Interface Function Figure 13-12: CAN Global Status Register (CGST) (2/2) Read (2/2) Bit Position Bit Name Function Indicates the global operating mode. 0: Access to CAN module registers is prohibited, except mask registers and Note 1 temporary buffers. 1: Operation of all CAN modules are enabled.
Page 401: Figure 13-13: Can Global Interrupt Enable Register (Cgie) (1/2)
Chapter 13 FCAN Interface Function CAN global interrupt enable register (CGIE) The CGIE register enables the global interrupts of the FCAN system. This register can be read in 1-bit, 8-bit and16-bit units. It can be written in 16-bit units only. For set- ting and clearing certain bits a special set/clear method applies.
Page 402 Chapter 13 FCAN Interface Function Figure 13-13: CAN Global Interrupt Enable Register (CGIE) (2/2) Write Bit Position Bit Name Function 15, 7 ST_G_IE7, Sets/clears the G_IE7 bit. CL_G_IE7 ST_G_IE7 CL_G_IE7 Status of G_IE7 Bit G_IE7 bit is cleared (0). G_IE7 bit is set (1). Others No change in G_IE7 bit value.
Page 403: Figure 13-14: Can Timer Event Enable Register (Cgten)
Chapter 13 FCAN Interface Function CAN timer event enable register (CGTEN) The CGTEN register enables/disables the 4 timer events. This register can read and written in 1-bit, 8-bit and 16-bit units. Figure 13-14: CAN Timer Event Enable Register (CGTEN) Address Initial Note Offset...
Page 404: Figure 13-16: Can Global Time System Counter (Cgtsc)
Chapter 13 FCAN Interface Function CAN global time system counter (CGTSC) The CGTSC register holds the value of the free-running 16-bit CAN global time system counter. (For details refer to chapters 13.2.3 Clock structure and 13.2.5 Time stamp) Note 1 This register can be read and written in 16-bit units only.
Page 405: Figure 13-17: Can Message Search Start Register (Cgmss)
Chapter 13 FCAN Interface Function CAN message search start register (CGMSS) The CGMSS register controls the start of a message search. It can be used for a fast message retrieval within the message buffers matching a search criteria (e.g. messages with DN flag set). This register is write-only and must be written in 16-bit units.
Page 406: Figure 13-18: Can Message Search Start Register (Cgmss)
Chapter 13 FCAN Interface Function CAN message search result register (CGMSR) The CGMSR register returns the result of a message search, started by writing the CGMSS regis- ter. This register is read-only and can be read in 1-bit, 8-bit and 16-bit units. Figure 13-18: CAN Message Search Start Register (CGMSS) Address Initial...
Page 407: Figure 13-19: Can Test Bus Register (Ctbr)
Chapter 13 FCAN Interface Function CAN test bus register (CTBR) For test purposes an internal test bus is available. The CTBR register controls this test bus capabil- ity. This register can be read and written in 8-bit and 16-bit units. Figure 13-19: CAN Test Bus Register (CTBR) Address Initial...
Page 408: Can Interrupt Pending Registers
Chapter 13 FCAN Interface Function 13.3.3 CAN interrupt pending registers CAN interrupt pending register (CCINTP) The CCINTP register summarizes all grouped interrupt pending signals. Each of them is assigned to an unambiguous interrupt vector of the V850E/CA1 (Atomic). This register is read-only and can be read in 8-bit and16-bit units. Figure 13-21: CAN Interrupt Pending Register (CCINTP) Address Initial...
Page 409: Figure 13-22: Can Global Interrupt Pending Register (Cgintp) (1/2)
Chapter 13 FCAN Interface Function CAN global interrupt pending register (CGINTP) The CGINTP register indicates the global interrupt pending signals. The interrupt pending flags can be cleared by writing to the register according to the special bit-clear method. (Refer to chapter 13.3.1) This register can be read in 8-bit and 16-bit units.
Page 410 Chapter 13 FCAN Interface Function Figure 13-22: CAN Global Interrupt Pending Register (CGINTP) (2/2) Write Bit Position Bit Name Function CL_GINT7 Clears the interrupt pending bit GINT7. 0: No change of GINT7 bit. 1: GINT7 bit is cleared (0). CL_GINT3 Clears the interrupt pending bit GINT3. 0: No change of GINT3 bit.
Page 411: Figure 13-23: Can 1 To 3 Interrupt Pending Registers (C1Intp To C3Intp) (1/2)
Chapter 13 FCAN Interface Function CAN 1 to 3 interrupt pending registers (C1INTP to C3INTP) The C1INTP to C3INTP registers indicate the corresponding CAN module interrupt pending sig- nals. The interrupt pending flags can be cleared by writing to the registers according to the special bit-clear method.
Page 412 Chapter 13 FCAN Interface Function Figure 13-23: CAN 1 to 3 Interrupt Pending Registers (C1INTP to C3INTP) (2/2) Read (2/2) Bit Name Bit Position Function Note CxINT1 Indicates a reception completion interrupt of CAN module x. 0: No Interrupt pending 1: Interrupt pending CxINT0 Indicates a transmission completion interrupt of CAN module x.
Page 413: Can Message Buffer Registers
Chapter 13 FCAN Interface Function 13.3.4 CAN message buffer registers Message identifier registers L00 to L63 and H00 to H63 (M_IDL00 to M_IDL63, M_IDH00 to M_IDH63) The M_IDLm, M_IDHm registers specify the identifier and format of the corresponding message m (m = 00 to 63).
Page 414: Figure 13-25: Message Configuration Registers 00 To 63 (M_Conf00 To M_Conf63)
Chapter 13 FCAN Interface Function Message configuration registers 00 to 63 (M_CONF00 to M_CONF63) The M_CONFm registers specify the message type, mask link and CAN module assignment of the corresponding message m (m = 00 to 63). These registers can be read/written 8-bit units. Figure 13-25: Message Configuration Registers 00 to 63 (M_CONF00 to M_CONF63) Address Note 1...
Page 415: Figure 13-26: Message Status Registers 00 To 63 (M_Stat00 To M_Stat63)
Chapter 13 FCAN Interface Function Message status registers 00 to 63 (M_STAT00 to M_STAT63) The M_STATm registers indicate transmit and receive status of the corresponding message m (m = 00 to 63). Bits can be set/cleared only by means of the SC_STATm register. These registers can be read-only in 8-bit units.
Page 416: Table 13-16: Can Message Processing By Trq And Rdy Bits
Chapter 13 FCAN Interface Function Processing of a transmit or receive message by TRQ and RDY flags is summarized in Table 13-16. Table 13-16: CAN Message Processing by TRQ and RDY Bits Message Type Message Processing × Message buffer is disabled for any processing by the assigned CAN module.
Page 417: Figure 13-27: Message Set/Clear Status Registers 00 To 63 (Sc_Stat00 To Sc_Stat63)
Chapter 13 FCAN Interface Function Message set/clear status registers 00 to 63 (SC_STAT0 to SC_STAT63) The SC_STATm registers set/clear the flags of the corresponding M_STATm registers (m = 00 to 63). By means of this register transmission can be requested and reception can be confirmed. These registers can be written-only in 16-bit units.
Page 418: Figure 13-28: Message Data Registers M0 To M7 (M_Datam0 To M_Datam7) (M = 00 To 63)
Chapter 13 FCAN Interface Function Message data registers m0 to m7 (M_DATAm0 to M_DATAm7) (m = 00 to 63) The M_DATAm0 to M_DATAm7 registers are used to hold the receive or transmit data of the corre- sponding message m (m = 00 to 63). These registers can be read/written in 8-bit units.
Page 419 Chapter 13 FCAN Interface Function Bit Position Bit Name Function 7 to 0 D0_7 to Contents of the message data byte 0. (first message data byte) (M_DATAm0) D0_0 7 to 0 D1_7 to Contents of the message data byte 1. (M_DATAm1) D1_0 7 to 0...
Page 420: Figure 13-29: Message Data Length Code Registers 00 To 63 (M_Dlc00 To M_Dlc63)
Chapter 13 FCAN Interface Function Message data length code registers 00 to 63 (M_DLC0 to M_DLC63) The M_DLCm registers specify the data length code (DLC) of the corresponding message m (m = 00 to 63). The DLC determines how many data bytes have to be transmitted, or received respectively, for the corresponding data frame.
Page 421: Figure 13-30: Message Control Registers 00 To 63 (M_Ctrl00 To M_Ctrl63) (1/2)
Chapter 13 FCAN Interface Function Message control registers 00 to 63 (M_CTRL0 to M_CTRL63) The M_CTRLm registers control the behaviour on reception or transmission of the corresponding message buffer m (m = 00 to 63). These registers can be read/written in 8-bit units. Figure 13-30: Message Control Registers 00 to 63 (M_CTRL00 to M_CTRL63) (1/2) Address Note...
Page 422 Chapter 13 FCAN Interface Function Figure 13-30: Message Control Registers 00 to 63 (M_CTRL00 to M_CTRL63) (2/2) Bit Position Bit Name Function Enables message buffer m related interrupts. 0: Interrupts related to message buffer m disabled. 1: Interrupts related to message buffer m enabled. Remark: If the message related interrupt is enabled, an interrupt is generated for any of the following conditions:...
Page 423: Figure 13-31: Message Time Stamp Registers 00 To 63 (M_Time00 To M_Time63)
Chapter 13 FCAN Interface Function Message time stamp registers 00 to 63 (M_TIME00 to M_TIME63) The M_TIMEm registers store the captured time stamp value on reception of the corresponding message m (m = 00 to 63). These registers can be read/written in 16-bit units. Figure 13-31: Message Time Stamp Registers 00 to 63 (M_TIME00 to M_TIME63) Address Initial...
Page 424: Figure 13-32: Message Event Registers M0, M1, And M3
Chapter 13 FCAN Interface Function Message event registers m0, m1, and m3 (M_EVTm0, M_EVTm1, M_EVTm3) (m = 00 to 63) The message event registers M_EVTm0, MEVTm1, and M_EVTm3 imply the event pointers for event processing with the CAN bridge ELISA (m = 0 to 63). These register can be read/written in 8-bit units.
Page 425: Can Module Registers
Chapter 13 FCAN Interface Function 13.3.5 CAN Module Registers CAN 1 to 3 mask 0 to 3 registers L, H (CxMASKL0 to CxMASKL3, CxMASKH0 to CxMASKH3) (x = 1 to 3) The CxMASKL0 to CxMASKL3, and CxMASKH0 to CxMASKH3 registers specify the four accept- ance masks for each CAN module x (x = 1 to 3).
Page 426: Table 13-17: Address Offsets Of The Can 1 To 3 Mask Registers
Chapter 13 FCAN Interface Function Table 13-17: Address Offsets of the CAN 1 to 3 Mask Registers Note 2 Address Offset Note Symbol x = 1 x = 2 x = 3 CxMASKL0 840H 880H 8C0H CxMASKH0 842H 882H 8C2H CxMASKL1 844H 884H...
Page 427: Figure 13-34: Can 1 To 3 Control Registers (C1Ctrl To C3Ctrl) (1/4)
Chapter 13 FCAN Interface Function CAN 1 to 3 control registers (C1CTRL to C3CTRL) The CxCTRL registers control the operating modes and indicate the operating status of the corre- sponding CAN module x (x = 1 to 3). These registers can be read in 8-bit and 16-bit units. It can be written in 16-bit units only. For setting and clearing certain bits a special set/clear method applies (refer to chapter 13.3.1).
Page 428 Chapter 13 FCAN Interface Function Figure 13-34: CAN 1 to 3 Control Registers (C1CTRL to C3CTRL) (2/4) Read (2/3) BOFF Indicates a bus-off status of the CAN module. 0: CAN module is not in bus-off state (transmission error counter < 256) 1: CAN module is in bus-off state (transmission error counter = 256) TSTAT Indicates the transmission status.
Page 429 Chapter 13 FCAN Interface Function Figure 13-34: CAN 1 to 3 Control Registers (C1CTRL to C3CTRL) (3/4) Read (3/3) STOP Selects the CAN stop mode. 0: CAN module is not stop mode. 1: CAN module stop mode selected. Remarks: 1. The CAN stop mode can be entered only if the CAN module is already in sleep mode (SLEEP = 1).
Page 430 Chapter 13 FCAN Interface Function Figure 13-34: CAN 1 to 3 Control Registers (C1CTRL to C3CTRL) (4/4) Write (2/2) Bit Position Bit Name Function 13, 5 ST_DLEVT, Sets/clears the DLEVT bit. CL_DLEVT ST_DLEVT CL_DLEVT Status of DLEVT bit DLEVT bit is cleared (0). DLEVT bit is set (1).
Page 431: Figure 13-35: Can 1 To 3 Definition Registers (C1Def To C3Def) (1/3)
Chapter 13 FCAN Interface Function CAN 1 to 3 definition registers (C1DEF to C3DEF) The CxDEF registers define normal and diagnostic operation and indicate CAN bus error and states of the corresponding CAN module x (x = 1 to 3). These registers can be read in 8-bit and 16-bit units.
Page 432 Chapter 13 FCAN Interface Function Figure 13-35: CAN 1 to 3 Definition Registers (C1DEF to C3DEF) (2/3) Read (2/2) Bit Position Bit Name Function SSHT Defines the single-shot mode for a CAN module. 0: Normal operating mode 1: Single-shot mode Remarks: 1.
Page 433 Chapter 13 FCAN Interface Function Figure 13-35: CAN 1 to 3 Definition Registers (C1DEF to C3DEF) (3/3) Write Bit Position Bit Name Function 15, 7 ST_DGM, Sets/clears the DGM bit. CL_DGM ST_DGM CL_DGM Status of DGM bit DGM bit is cleared (0). DGM bit is set (1).
Page 434: Figure 13-36: Can 1 To 3 Information Registers (C1Last To C3Last)
Chapter 13 FCAN Interface Function CAN 1 to 3 information registers (C1LAST to C3LAST) The CxLAST registers return the number of the last received message and last CAN protocol error of the corresponding CAN module x (x = 1 to 3). These registers can be read-only in 8-bit and 16-bit units.
Page 435: Figure 13-37: Can 1 To 3 Error Counter Registers (C1Erc To C3Erc)
Chapter 13 FCAN Interface Function CAN 1 to 3 error counter registers (C1ERC to C3ERC) The CxERC registers reflect the status of the transmit and the receive error counters of the corre- sponding CAN module x (x = 1 to 3). These registers can be read-only in 8-bit and 16-bit units.
Page 436: Figure 13-38: Can 1 To 3 Interrupt Enable Registers (C1Ie To C3Ie) (1/2)
Chapter 13 FCAN Interface Function CAN 1 to 3 interrupt enable registers (C1IE to C3IE) The CxIE registers enable the transmit, receive and error interrupts of the corresponding CAN mod- ule x (x = 1 to 3). These registers can be read in 8-bit and 16-bit units. It can be written in 16-bit units only. For setting and clearing certain bits a special set/clear method applies (refer to chapter 13.3.1).
Page 437 Chapter 13 FCAN Interface Function Figure 13-38: CAN 1 to 3 Interrupt Enable Registers (C1IE to C3IE)(2/2) Write Bit Position Bit Name Function 14, 6 ST_E_INT6, Sets/clears the E_INT6 bit. CL_E_INT6 ST_E_INT6 CL_E_INT6 Status of E_INT6 bit E_INT6 bit is cleared (0). E_INT6 bit is set (1).
Page 438: Figure 13-39: Can 1 To 3 Bus Activity Registers (C1Ba To C3Ba) (1/2)
Chapter 13 FCAN Interface Function CAN 1 to 3 bus activity registers (C1BA to C3BA) The CxBA registers indicate the status of the CAN bus activities of the corresponding CAN module x (x = 1 to 3). These registers can be read-only in 8-bit and 16-bit units. Figure 13-39: CAN 1 to 3 Bus Activity Registers (C1BA to C3BA) (1/2) Address Initial...
Page 439 Chapter 13 FCAN Interface Function Figure 13-39: CAN 1 to 3 Bus Activity Registers (C1BA to C3BA) (2/2) Bit Position Bit Name Function 7 to 0 TMNO7 to Indicates the message buffer, which is either waiting to be transmitted or in transmis- TMNO0 sion progress.
Page 440: Figure 13-40: Can 1 To 3 Bit Rate Prescaler Registers (C1Brp To C3Brp) (1/2)
Chapter 13 FCAN Interface Function CAN 1 to 3 bit rate prescaler registers (C1BRP to C3BRP) The CxBRP registers specify the bit rate prescaler and CAN bus speed of the corresponding CAN module x (x = 1 to 3). The register layout depends on the TLM bit (bit 15), and distinguishes between 6-bit prescaler (TLM bit = 0) and 8-bit prescaler (TLM bit = 1).
Page 441 Chapter 13 FCAN Interface Function Figure 13-40: CAN 1 to 3 Bit Rate Prescaler Registers (C1BRP to C3BRP) (2/2) Bit Position Bit Name Function 7 to 0 BRP7 to Specifies the bit rate prescaler for the CAN protocol layer. (TLM = 1) BRP0 TLM = 0: (TLM = 1)
Page 442: Figure 13-41: Can Bus Bit Timing
Chapter 13 FCAN Interface Function CAN 1 to 3 synchronization control registers (C1SYNC to C3SYNC) A bit in a CAN frame is built by a programmable number of time quanta (TQ), as shown in the Fig- ure 13-41 below. Figure 13-41: CAN Bus Bit Timing SYNC_SEG PROP_SEG PHASE_SEG1...
Page 443: Figure 13-42: Can 1 To 3 Synchronization Control Registers (C1Sync To C3Sync) (1/2))
Chapter 13 FCAN Interface Function The CxSYNC registers specify the data bit time (DBT), sampling point position (SPT) and synchro- nisation jump width (SJW) of the corresponding CAN module x (x = 1 to 3). These registers can be read/written in 8-bit and 16-bit units. However, write access is only permitted in initialisation mode (ISTAT bit of the CxCTRL register = 1) Figure 13-42: CAN 1 to 3 Synchronization Control Registers (C1SYNC to C3SYNC) (1/2)) Address...
Page 444 Chapter 13 FCAN Interface Function Figure 13-42: CAN 1 to 3 Synchronization Control Registers (C1SYNC to C3SYNC) (2/2) Bit Position Bit Name Function 4 to 0 DBT4 to Specifies the number of TQ per bit. DBT0 Data Bit Time DBT4 DBT3 DBT2 DBT1...
Page 445: Figure 13-43: Can 1 To 3 Bus Diagnostic Information Registers (C1Dinf To C3Dinf)
Chapter 13 FCAN Interface Function (10) CAN 1 to 3 bus diagnostic information registers (C1DINF to C3DINF) The CxDINF registers reflect the last transmission on CAN bus of the corresponding CAN module x (x = 1 to 3). These registers can be read-only in 1-bit, 8-bit and 16-bit units. It is only accessible when diagnostic mode is set (CxDEF register’s MOM bit = 1).
Page 446: Operating Condsiderations
Chapter 13 FCAN Interface Function 13.4 Operating Condsiderations 13.4.1 Rules to be observed for correct baud rate settings Observing the following rules for the baud rate setting assures correct operation of a CAN module and compliance to the CAN protocol specification. Rule for sampling point (SPT) setting: The sample point position needs to be programmed between 3 TQ and 17 TQ, which corresponds to the SPT4 to SPT0 bits of the CxSYNC register (x = 1 to 3):...
Page 447: Example For Baudrate Setting Of Can Module
Chapter 13 FCAN Interface Function 13.4.2 Example for baudrate setting of CAN module To illustrate how to calculate the correct setting of the registers CxBRP and CxSYNC the following example is given to 3: Requirements from CAN bus: - FCAN system global frequency f = 16 MHz - CAN bus baud rate f = (83...
Page 448 Chapter 13 FCAN Interface Function Regarding the maximum sampling point setting and the resulting sampling point, two settings meet all the requirements above. Therefore the correct settings are: TLM=0: BRP5 to BRP0 = 000101B (5) (prescaler BRP = 12 TQ) DBT4 to DBT0 = 01111B (15) (data bit time DBT = 16 TQ) SPT4 to SPT0 =...
Page 449: Ensuring Data Consistency
Chapter 13 FCAN Interface Function 13.4.3 Ensuring data consistency If the CPU reads data from the CAN message buffers, the consistency of data read has to be ensured. Therefore two mechanisms are provided: • Sequential data read • Burst mode data read Sequential data read If the data is read by the CPU by sequential accesses to the CAN message buffers, the following sequence has to be observed:...
Page 450 Chapter 13 FCAN Interface Function Burst Mode Data Read For faster access to a complete message the burst read mode is applicable. In burst read mode the complete message is copied from the internal message buffer to a tempo- rary read buffer located outside the CAN memory section. This allows read access without any wait, if the CAN memory is accessed by the CAN modules while the CPU tries to read data.
Page 451: Operating States Of The Can Modules
Chapter 13 FCAN Interface Function 13.4.4 Operating states of the CAN modules The different operating states and the state transitions of the CAN modules are shown in the state transition diagram in Figure 13-45. Figure 13-45: State Transition Diagram for CAN Modules Initialisation Mode INIT = 0 CxCTRL[ ISTAT ] =1...
Page 452: Initialisation Routines
Chapter 13 FCAN Interface Function 13.4.5 Initialisation routines Below the necessary steps for correct start-up of the CAN interface are explained. Caution: It is very important that the software programmer observes the sequence given in the following paragraphs. Otherwise unexpected operation of the CAN interface or any CAN module can occur.
Page 453 Chapter 13 FCAN Interface Function Example for C routine: int CAN_GlobalInit (void) unsigned char i; CGST = 0x00FF; // clear all flags of CGST CGIE = 0x00FF; // disable global interrupts CGCS = 0x0000; // define internal clock CGTSC = 0x0000; // clear CAN global time system counter CGTEN = 0x0000;...
Page 454: Figure 13-47: Initialisation Sequence For A Can Module
Chapter 13 FCAN Interface Function Initialisation sequence for a CAN Module Each CAN module must be initialised by the sequence according to Figure 13-47. Figure 13-47: Initialisation Sequence for a CAN module INIT CAN MODULE Init the module registers: - CxCTRL (but do not clear the INIT flag) - CxDEF - CxIE...
Page 455 Chapter 13 FCAN Interface Function Example for C routine: int CAN_ModuleInit (unsigned char module_no, unsigned short brp_value, unsigned short sync_value) can_module_type *can_mod_ptr; // define ptr can_mod_ptr = &can_module[module_no]; // load ptr can_mod_ptr->CxCTRL = 0x00FE; // clear CxCTRL // except INIT can_mod_ptr->CxDEF = 0x00FF;...
Page 456: Figure 13-48: Setting Can Module Into Initialisation State
Chapter 13 FCAN Interface Function Setting a CAN Module into initialisation state The following routine is required if a CAN module has to be set from normal operation into initialisa- tion mode. Please notice that all CAN modules are automatically set to initialisation mode after reset. There- fore the sequence is only required if the CAN module is already in normal operation.
Page 457 Chapter 13 FCAN Interface Function Shutdown of the FCAN system If the clock to the CAN interface should be switched off for power saving, the following sequence has to be executed for correct termination of any CAN bus activity: <1> For each CAN module x (x = 1 to 3) <a>...
Page 458: Can Bridge Elisa
Chapter 13 FCAN Interface Function 13.5 CAN Bridge ELISA 13.5.1 Principle of operation ELISA is the name of an event processor, a sophisticated machine that supports the CPU on data transfer between different CAN buses and on time management functions. The operations done by ELISA are based on user-programmable sequences of commands.
Page 459: Figure 13-49: Main Operation Of Elisa
Chapter 13 FCAN Interface Function Operation Flow Charts For better understanding the following flow charts will explain how ELISA operates. Figure 13-49: Main Operation of ELISA ELISA MAIN timer event pending? msg. event pending? script event Load source pending? message and set type of event Load command Load Command...
Page 460: Figure 13-50: Event Processing By Elisa
Chapter 13 FCAN Interface Function Figure 13-50: Event Processing by ELISA Start Event Processing Message Event? Cnt = Temporary CNT = 0 event pointer Load and execute command - Allow other Execution modules to access Error? CAN Memory END bit set? CNT = CNT+1 CNT >...
Page 461: Figure 13-51: End Of Event Processing
Chapter 13 FCAN Interface Function Figure 13-51: End of Event Processing End Event Processing message event? new source loaded? Clear: Clear internal - ERQ flag of message ERQ flag - temporary message event temporary pointer Source modified? Write ELISA source buffer to Message Buffer ELISA MAIN Preliminary User’s Manual U14913EE1V0UM00...
Page 462: Figure 13-52: Example For Event Processing Of Elisa
Chapter 13 FCAN Interface Function Example As an example for message event processing please look at the Figure 13-52 below. A message requires event processing of ELISA. Therefore a set of commands for that event processing is defined in the command list section, and the event pointer of the message contains the number of the first com- mand ELISA should execute whenever the event processing for the message is requested.
Page 463 The used programming tool has to observe that the code generated for ELISA meets the specifica- tion of the ELISA commands. Any command not meeting the command requirements leads into malfunction of ELISA. The programming tools provided by NEC take care that no commands with illegal parameters are generated. Preliminary User’s Manual U14913EE1V0UM00...
Page 464: Implementation Details
Chapter 13 FCAN Interface Function 13.5.2 Implementation details The event pointers are used to indicate the start of a command sequence that should be executed whenever an event occurs. If ELISA detects an ERQ flag for a message buffer, it loads the related event pointer.
Page 465: Figure 13-53: Elisa Command Format
Chapter 13 FCAN Interface Function Command format Each action command consists of a 32-bit word of the following format. Figure 13-53: ELISA Command Format END EHDL COND CMD4 CMD3 CMD2 CMD1 CMD0 DEST7 DEST6 DEST5 DEST4 DEST3 DEST2 DEST1 DEST0 PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PAR9 PAR8 PAR7 PAR6 PAR5 PAR4 PAR3 PAR2 PAR1 PAR0 Bit Position Bit Name...
Page 466 Chapter 13 FCAN Interface Function Bit location definition for bit commands If the location of a bit or a bit-string has to be defined for a command, the bit location is given as a 6- bit or 5-bit value (named in to following as “BIT_POS”) using the following formula. If a 6-bit value is given, the location is absolute without any offset for the byte location.
Page 467 Chapter 13 FCAN Interface Function ELISA specific events (a) Timer event processing by ELISA There are four timer events available (periodic intervals). Each of the timer events can be enabled or disabled individually. Whenever a timer event occurs, the event is reported to ELISA. ELISA will start the event processing similar to events given by messages, but the event pointers are read from pointer buffers located in ELISA.
Page 468: Event Processing Commands
Chapter 13 FCAN Interface Function 13.5.3 Event processing commands Command Overview Code Description Mnemonic no operation NOP 0,0 define and load new source SET_SRC <DEST>,<PAR> set script event SET_EVT <DEST>,0 generate interrupt and stop operation BREAK 0,0 04H to reserved for future implementations write value to counter SET_CNT <DEST>,<PAR>...
Page 469 Chapter 13 FCAN Interface Function (a) No operation (NOP) Command No Operation Code Mnemonic NOP 0,0 (b) Define and load new source (SET_SRC) Command Define and Load New Source Code Mnemonic SET_SRC <DEST>,<PAR> DEST7 to Destination DEST0 0 to 255 Number of new source message PAR0 Parameter...
Page 470 Chapter 13 FCAN Interface Function (e) Set Counter (SET_CNT) Command Set Counter Code Mnemonic SET_CNT <DEST>,<PAR> DEST2 to Destination DEST0 0 to 7 Number of counter PAR7 to Parameter PAR0 0 to 255 Value written to counter (f) Decrement counter and update CFLG flag (DECR_CNT) Command Decrement Counter and Update CFLG Flag Code...
Page 471 Chapter 13 FCAN Interface Function (g) Test Source Bit and Update CFLG Flag (TST_BIT) Command Decrement Counter and Update CFLG Flag Code Mnemonic TST_BIT <DEST>,<PAR> Remark: The test bit number is set as described in 13.5.2 (3)Bit location definition for bit commands DEST5 to Destination DEST0...
Page 472 Chapter 13 FCAN Interface Function (h) Set and/or clear message flags (WR_FLG) Command Set and/or Clear Message Flags (M_STATm Register) Code Mnemonic WR_FLG <DEST>,<PAR> DEST5 to Destination DEST0 0 to 254 Destination message number (absolute) Manipulate message flags (in M_STATm register) of source message PAR15 to Parameter (Upper Byte) PAR8...
Page 473 Chapter 13 FCAN Interface Function (j) Write source data to destination data bytes 0 to 3 (WR_DLO) Command Write Source Data to Destination Data Bytes 0 to 3 Code Mnemonic WR_DLO <DEST>,<PAR> DEST7 to Destination DEST0 0 to 255 Number of message buffer the command uses as target PAR15 to Parameter for Destination Data Byte 0 PAR12...
Page 474 Chapter 13 FCAN Interface Function (k) Write source data to destination data bytes 4 to 7 (WR_DHI) Command Write Source Data to Destination Data Bytes 4 to 7 Code Mnemonic WR_DHI <DEST>,<PAR> DEST7 to Destination DEST0 0 to 255 Number of message buffer the command uses as target PAR15 to Parameter for Destination Data Byte 4 PAR12...
Page 475 Chapter 13 FCAN Interface Function (l) Copy all source data to destination (WR_DALL) Command Copy All Source Data to Destination (Including DLC) Code Mnemonic WR_DALL <DEST>,<PAR> DEST7 to Destination DEST0 0 to 255 Number of message buffer the command uses as target PAR0 Parameter Copy all data except source identifier to destination...
Page 476 Chapter 13 FCAN Interface Function (n) Write source bit-string to destination bit-string, data bytes 4 to 7 (WR_DBHI) Command Write Source Data to Destination Bit-string, Data Bytes 4 to 7 Code Mnemonic WR_DBHI <DEST>,<PAR> DEST7 to Destination DEST0 0 to 255 Number of message buffer the command uses as target PAR14 to Parameter for Start Position in Source...
Page 477 Chapter 13 FCAN Interface Function (o) Get data bytes from destination data bytes 0 to 3 (LD_DLO) Command Get Data Bytes from Destination Data Bytes 0 to 3 Code Mnemonic LD_DLOI <DEST>,<PAR> DEST7 to Destination DEST0 0 to 255 Number of message buffer the command uses as target PAR15 to Parameter for Destination Data Byte 0 PAR12...
Page 478 Chapter 13 FCAN Interface Function (p) Get data bytes from destination data bytes 4 to 7 (LD_DHI) Command Get Data Bytes from Destination Data Bytes 4 to 7 Code Mnemonic LD_DHI <DEST>,<PAR> DEST7 to Destination DEST0 0 to 255 Number of message buffer the command uses as target PAR15 to Parameter for Destination Data Byte 4 PAR12...
Page 479 Chapter 13 FCAN Interface Function (q) Get source bit-string from destination bit-string, data bytes 0 to 3 (LD_DBLO) Command Get Source Bit-string from Destination Bit-string, Data Bytes 0 to 3 Code Mnemonic LD_DBLO <DEST>,<PAR> DEST7 to Destination DEST0 0 to 255 Number of message buffer the command uses as target PAR14 to Parameter for Start Position in Source...
Page 480: Figure 13-54: Timer Event Pointer Registers 0, 1 And 3 (Tep0, Tep1, Tep3)
Chapter 13 FCAN Interface Function ELISA Register Area (a) Timer event pointer registers 0, 1 and 3 (TEP0, TEP1, TEP3) The TEPn registers set the corresponding timer event pointers (n = 0, 1, 3). This register can be read and written in 8-bit units only. Figure 13-54: Timer Event Pointer Registers 0, 1 and 3 (TEP0, TEP1, TEP3) Address Note...
Page 481: Figure 13-55: Script Event Pointer And Command Counter Register (Sepcc)
Chapter 13 FCAN Interface Function (b) Script event pointer and command counter register (SEPCC) The SEPCC register controls the script pointer and commands This register can be read and written in 8-bit and 16-bit units. Figure 13-55: Script Event Pointer And Command Counter Register (SEPCC) Address Initial Note...
Page 482: Figure 13-56: Elisa Event Processing Status Register (Eeps)
Chapter 13 FCAN Interface Function (c) ELISA event processing status register (EEPS) The EEPS register indicates the ELISA processing status. This register can be read and written in 8-bit and 16-bit units. Figure 13-56: ELISA Event Processing Status Register (EEPS) Address Initial Note...
Page 483: Figure 13-57: Elisa Event Processing Status Register (Elsr) (1/2)
Chapter 13 FCAN Interface Function (d) ELISA status register (ELSR) The ELSR register indicates the ELISA status. The bits 7 to 0 can be set and cleared by writing to the register according to the special bit-set/clear method. (Refer to chapter 13.3.1) This register can be read in 8-bit and 16-bit units.
Page 484 Chapter 13 FCAN Interface Function Figure 13-57: ELISA Event Processing Status Register (ELSR) (2/2) Read Bit Position Bit Name Function PTE2 Indicates a pending timer event 2. 0: Timer event 2 is not pending. 1: Timer event 2 is pending. PTE1 Indicates a pending timer event 1.
Page 485: Figure 13-58: Elisa Last Processed Command Register (Elc)
Chapter 13 FCAN Interface Function (e) ELISA last processed command register (ELC) The ELC register indicates the upper 16-bit of the last processed command by ELISA. The register is can be read in 16-bit units only. Figure 13-58: ELISA Last Processed Command Register (ELC) Address Initial Note...
Page 486: Figure 13-59: Elisa Temporary Buffer Registers (Etbl, Etbh)
Chapter 13 FCAN Interface Function (f) ELISA temporary buffer registers (ETBL, ETBLH) The ETBL and ETBH registers contain the temporary buffer The registers can be read and written in 8-bit and 16-bit units. Figure 13-59: ELISA Temporary Buffer Registers (ETBL, ETBH) Address Initial Note...
Page 487: Chapter 14 A/D Converter
Chapter 14 A/D Converter 14.1 Features • 10-bit resolution on-chip A/D converter • Analog inputs: 12 channels • Separate on-chip A/D conversion result registers for each analog input - 10 bits × 12 registers • A/D conversion trigger modes - A/D trigger mode - A/D trigger polling mode - Timer trigger mode •...
Page 488: Configuration
Chapter 14 A/D Converter 14.2 Configuration The A/D converter, which employs a successive approximation technique, performs A/D conversion operation using A/D scan mode registers 0 and 1 (ADSCM0, ADSCM1) and A/D conversion result reg- isters ADCRm (m = 0 to 11). Input circuit The input circuit selects an analog input (ANIm) according to the mode set in the ADSCM0 register and sends it to the sample and hold circuit (m = 0 to 11).
Page 489 Chapter 14 A/D Converter The AV pin is used to input reference voltage to the A/D converter. A signal input to the ANIm pin is converted to a digital signal based on the voltage applied between AV and AV Note (m = 0 to 11).
Page 490: Figure 14-1: Block Diagram Of A/D Converter
Chapter 14 A/D Converter Figure 14-1: Block Diagram of A/D Converter ANI0 ANI1 ANI2 ANI3 Comparator Sample and and D/A ANI4 hold circuit converter ANI5 ANI11 SAR (10) INTAD ADCR0 Controller ADCR1 INTPE10/TINTCCE10 ADCR2 INTDET ADCR3 ADCR4 ADCR5 ADCR11 ADSCM0 (16) ADSCM1 (16) ADETM (16) Internal bus...
Page 491: Control Registers
Chapter 14 A/D Converter 14.3 Control Registers A/D scan mode register 0 (ADSCM0) The ADSCM0 register is a 16-bit register that selects analog input pins, specifies operation modes, and controls conversion operation. It can be read or written in 1-bit, 8-bit or 16-bit units. However, writing to the ADSCM0 register dur- ing A/D conversion operation interrupts the conversion operation and the data is lost.
Page 492 Chapter 14 A/D Converter Figure 14-2: A/D Scan Mode Register 0 (ADSCM0) (2/2) Bit position Bit name Function 7 to 4 SANI3 to The bits SANI3 to SANI0 specify the analog input pin mode for which the 1st conversion is SANI0 performed in scan mode.
Page 493: Figure 14-3: A/D Scan Mode Register 1 (Adscm1)
Chapter 14 A/D Converter A/D scan mode register 1 (ADSCM1) The ADSCM1 register is a 16-bit register that sets the conversion time of the A/D converter. It can be read or written in 1-bit, 8-bit, or 16-bit units. Figure 14-3: A/D Scan Mode Register 1 (ADSCM1) Address Initial value...
Page 494 Chapter 14 A/D Converter (a) Conversion time setting In order to prevent a drastic change of A/D conversion time even when the oscillation frequency is changed, the conversion speed of an operation stage can be adjusted. By the selection bits FR2 to FR0 in the ADSCM1 register the SAR compare time T can be set in the range of 20/f to 140/f...
Page 495 Chapter 14 A/D Converter (b) Start of conversion trigger setup timing When starting the start of conversion by internal timer interrupt signal (TINTCCE10) an additional setup time T of 8 system clocks has to be considered. TRGAD ⁄ TRGAD Thus the total time of A/D conversion T including the trigger setup time is as follows.
Page 496: Figure 14-4: A/D Voltage Detection Mode Register (Adetm)
Chapter 14 A/D Converter A/D voltage detection mode register (ADETM) The ADETM register is a 16-bit register that sets voltage detection mode. In voltage detection mode a reference voltage value is compared with the analog input pin for which voltage detection is being performed, and an interrupt is set in response to the comparison result.
Page 497: Figure 14-5: A/D Conversion Result Registers 0 To 11 (Adcr0 To Adcr11)
Chapter 14 A/D Converter A/D conversion result registers 0 to 11 (ADCR0 to ADCR11) The ADCRm registers are 10-bit registers that hold the results of A/D conversions (m = 0 to 11). These registers can only be read in 16-bit units. When reading 10 bits of data of an A/D conversion result from an ADCRm register, only the lower 10 bits are valid and the upper 6 bits always read 0.
Page 498: Figure 14-6: Relationship Between Analog Input Voltages And A/D Conversion Results
Chapter 14 A/D Converter The correspondence between each analog input pin and the ADCRm registers is shown in Table 14-2. Table 14-2: Correspondence between each Analog Input Pin and ADCRm Registers Analog Input Pin A/D Conversion Result Register ANI0 ADCR0 ANI1 ADCR1 ANI2...
Page 499: Interrupt Requests
Chapter 14 A/D Converter 14.4 Interrupt Requests The A/D converter generates two kinds of interrupts. • A/D conversion termination interrupt (INTAD) • Voltage detection interrupt (INTDET) A/D conversion termination interrupt (INTAD) In A/D conversion enabled status, an A/D conversion termination interrupt is generated when a specified number of A/D conversions have terminated.
Page 500: A/D Converter Operation
Chapter 14 A/D Converter 14.5 A/D Converter Operation 14.5.1 A/D converter basic operation A/D conversion is performed using the following procedure. (1) Set the analog input selection and the operation mode and trigger mode specifications using the Note 1 ADSCM0 .
Page 501: Operation Modes And Trigger Modes
Chapter 14 A/D Converter 14.5.2 Operation modes and trigger modes Several conversion operations can be specified for A/D converter by specifying operation modes and trigger modes. Operation modes and trigger modes are set using the ADSCM0 register. The relationship between operation modes and trigger modes is shown below. Trigger Mode Operation Mode Setting of ADSCM0...
Page 502: Figure 14-7: Example Of Select Mode Operation Timing (Ani1)
Chapter 14 A/D Converter Operation modes The two operation modes are select mode and scan mode. These modes are set using the ADSCM0 register. (a) Select mode In select mode the A/D converts one analog input specified in the ADSCM0 register. The conver- sion result is stored in the ADCRm register corresponding to the analog input (ANIm) (m = 0 to 11).
Page 503: Figure 14-8: Example Of Scan Mode Operation Timing (4-Channel Scan (Ani0 To Ani3))
Chapter 14 A/D Converter (b) Scan mode The scan mode sequentially selects and converts pin input voltage from the A/D conversion start analog input pin through the A/D conversion termination analog input pin specified in the ADSCM0 register. It stores the A/D conversion result in the ADCRm register corresponding to the analog input (m = 0 to 11).
Page 504: Operation In A/D Trigger Mode
Chapter 14 A/D Converter 14.6 Operation in A/D Trigger Mode Setting the CE bit of the ADSCM0 register to 1 starts A/D conversion immediately. 14.6.1 Operation in select mode One analog input specified in the ADSCM0 register is A/D converted at a time and the result is stored in an ADCRm register.
Page 505: Operation In Scan Mode
Chapter 14 A/D Converter 14.6.2 Operation in scan mode The pins from the first analog input pin through the last analog input pin, specified in the ADSCM0 reg- ister, are sequentially selected and A/D converted. The A/D conversion result is stored in the ADCRm register corresponding to the analog input (m = 0 to 11).
Page 506: Operation In A/D Trigger Polling Mode
Chapter 14 A/D Converter 14.7 Operation in A/D Trigger Polling Mode Setting the CE bit of the ADSCM0 register to 1 starts the A/D conversion immediately. Both select mode and scan mode can be continued with A/D trigger polling mode. Since the CS bit of the ADSCM0 register remains 1 after an INTAD interrupt in this mode, it is not necessary to set the CE bit to restart the A/D conversion.
Page 507: Operation In Scan Mode
Chapter 14 A/D Converter 14.7.2 Operation in scan mode The pins from the first analog input pin through the last analog input pin, specified in the ADSCM0 reg- ister, are sequentially selected and A/D converted. The A/D conversion result is stored in the ADCRm register corresponding to the analog input (m = 0 to 11).
Page 508: Operation In Timer Trigger Mode
Chapter 14 A/D Converter 14.8 Operation in Timer Trigger Mode The A/D converter can set an interrupt signal as a conversion trigger for up to 12 channels of analog input (ANI0 to ANI11). The interrupt signal that can be selected as trigger is the Timer E 0 interrupt INTPE10/TINTCCE10. 14.8.1 Operation in select mode One analog input (ANI0 to ANI) specified by the ADSCM0 register is A/D converted.
Page 509: Operation In Scan Mode
Chapter 14 A/D Converter 14.8.2 Operation in scan mode Analog input pins specified by register ADSCM0 are selected sequentially, and the specified number of A/D conversions are performed by using the Timer E 0 interrupt as a trigger. The conversion results are stored in the ADCRm registers corresponding to the analog inputs (m = 0 to 11).
Page 510: Figure 14-14: Example Of Timer Trigger Scan Mode Operation (Ani1 To Ani4)
Chapter 14 A/D Converter Figure 14-14: Example of Timer Trigger Scan Mode Operation (ANI1 to ANI4) ANI0 ADCR0 ANI1 ADCR1 INTPE10/TINTCCE10 ANI2 ADCR2 A/D converter ANI3 ADCR3 ANI4 ADCR4 ANI5 ADCR5 ANI11 ADCR11 (1) CE bit of ADSCM0 = 1 (Enabled) (7) A/D conversion of ANI3 (2) INTPE10/TINTCCE10 interrupt generation (8) Store conversion result in ADCR3...
Page 511: Precautions
Chapter 14 A/D Converter 14.9 Precautions 14.9.1 Stopping conversion operation If the CE bit of the ADSCM0 register is cleared during conversion operation, all conversion operations are stopped, and a conversion result is not stored in the ADCRm register (m = 0 to 11). 14.9.2 Trigger input during conversion operation If a trigger is input during conversion operation, that trigger input is ignored.
Page 512 [MEMO] Preliminary User’s Manual U14913EE1V0UM00...
Page 513: Chapter 15 Lcd Controller/Driver
Chapter 15 LCD Controller/Driver 15.1 LCD Controller/Driver Functions The functions of the LCD controller/driver incorporated in the µPD70F3123 subseries are shown below. (1) Automatic output of segment signals and common signals is possible by automatic reading of the display data memory. (2) Display mode - 1/4 duty (1/3 bias) (3) Any of four frame frequencies can be selected in each display mode.
Page 514: Figure 15-1: Lcd Controller/Driver Block Diagram
Chapter 15 LCD Controller/Driver Figure 15-1: LCD Controller/Driver Block Diagram Display Prescaler Data Memory CKSEL1 Segment Timing Controller Data Selector LCD Drive Voltage Generator Segment Driver Common Driver S30 ... S0 ... S10 ... COM0 COM2 LCD0 LCD1 LCD2 COM1 COM3 Note: Segment driver Figure 15-2: LCD Clock Select Circuit Block Diagram...
Page 515: Lcd Controller/Driver Control Registers
Chapter 15 LCD Controller/Driver 15.3 LCD Controller/Driver Control Registers The LCD controller/driver is controlled by the following register. • LCD display mode register (LCDM) LCD display mode register (LCDM) This register sets display operation enabling/disabling, the LCD clock, frame frequency. The LCDM register can be read or written in 1-bit or 16-bit units.
Page 516: Figure 15-4: Port Lcd Segment Selector Registers 0 To 4 (Lseg0 To Lseg4)
Chapter 15 LCD Controller/Driver Port LCD segment selector registers 0 to 4 (LSEG0 to LSEG4) The LSEG0 to LSEG4 registers control the pin function of the corresponding pins. These registers can be read or written in 1-bit or 8-bit units. Figure 15-4: Port LCD Segment Selector Registers 0 to 4 (LSEG0 to LSEG4) Address At Reset...
Page 517: Lcd Memory Layout
Chapter 15 LCD Controller/Driver 15.4 LCD Memory Layout The LCD display data memory is mapped onto addresses 3FFF720H to 3FFF746H. The data stored in the LCD display data memory can be displayed on an LCD panel by the LCD controller/driver. Table 15-3 shows the relationship between the LCD display data memory contents and the segment outputs/common outputs.
Page 518: Common Signals And Segment Signals
Chapter 15 LCD Controller/Driver 15.5 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the LCD drive voltage VLCD). The light goes off when the potential difference becomes VLCD or lower.
Page 519: Figure 15-5: Common Signal Waveform
Chapter 15 LCD Controller/Driver “Common Signal Waveform” on page 519 shows the common signal waveform, and “Common Signal and Segment Signal Voltages and Phases” on page 519 shows the common signal and segment signal voltages and phases. Figure 15-5: Common Signal Waveform COMn (Divided by 4) = 4 x T...
Page 520: Supplying Lcd Drive Voltage
Chapter 15 LCD Controller/Driver 15.6 Supplying LCD Drive Voltage V , and V The µPD703123 Subseries have a split resistor to create an LCD drive voltage, and the drive voltage is fixed to 1/3 bias. To supply various LCD drive voltages, internal V or external V supply voltage can be selected.
Page 521: Figure 15-7: Example Of Connection Of Lcd Drive Power Supply
Chapter 15 LCD Controller/Driver “Example of Connection of LCD Drive Power Supply” on page 521 shows an example of supplying an LCD drive voltage from an internal source according to “Drive Voltage Supply” on page 520 By using variable resistors r1 and r2, a non-stepwise LCD drive voltage can be supplied. Figure 15-7: Example of Connection of LCD Drive Power Supply (a) To supply LCD drive voltage from V LIPS (= 1)
Page 522: Display Mode
Chapter 15 LCD Controller/Driver 15.7 Display Mode 15.7.1 4-time-division display example Figure 15-9 shows the connection of a 4-time-division type 10-digit LCD panel with the display pattern shown in Figure 15-8 with the µPD703123 Subseries segment signals (S0 to S19) and common signals (COM0 to COM3).
Page 523: Figure 15-9: 4-Time-Division Lcd Panel Connection Example
Chapter 15 LCD Controller/Driver Figure 15-9: 4-Time-Division LCD Panel Connection Example COM3 COM2 COM1 COM0 Preliminary User’s Manual U14913EE1V0UM00...
Page 524: Figure 15-10: 4-Time-Division Lcd Drive Waveform Examples (1/3 Bias Method)
Chapter 15 LCD Controller/Driver Figure 15-10: 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) COM0 COM1 COM2 COM3 +1/3V COM0 to S8 –1/3V –V +1/3V COM1 to S8 –1/3V –V Preliminary User’s Manual U14913EE1V0UM00...
Page 525: Chapter 16 Port Functions
Chapter 16 Port Functions 16.1 Features • Input/Output ports: 90 • Ports alternate as input/output pins of other peripheral functions • Input or output can be specified in bit units Preliminary User’s Manual U14913EE1V0UM00...
Page 526: Port Configuration
Chapter 16 Port Functions 16.2 Port Configuration The V850E/CA1 incorporates a total of 90 input/output ports, named ports P1 through P6, and PAL, PAH, PDL, PCS, PCT and PCM. The configuration is shown below. PAL0 Port 1 Port AL PAL15 PAH0 Port 2 Port AH...
Page 527 Chapter 16 Port Functions Functions of each port The V850E/CA1 has the ports shown below. Any port can operate in 8- or 1-bit units and can provide a variety of controls. Moreover, besides its function as a port, each has functions as the input/output pins of on-chip peripheral I/O in control mode.
Page 528 Chapter 16 Port Functions Functions of each port pin on reset and registers that set port or control mode Port Name Pin Name Pin Function after Reset Mode-Setting Register Single-Chip Mode Port 1 P10/CRXD1 P10 (Input mode) PMC1 P11/CTXD1 P11 (Input mode) P12/CRXD2 P12 (Input mode) P13/CTXD2...
Page 529 Chapter 16 Port Functions Port Name Pin Name Pin Function after Reset Mode-Setting Register Single-Chip Mode Port 6 P60/CCLK/SEG34 P60 (Input mode) PMC6 P61/INT0/SEG35 P61 (Input mode) P62/INT1/SEG36 P62 (Input mode) P63/INT2/SEG37 P63 (Input mode) P64/RXD2/SEG38 P64 (Input mode) P65/TXD2/SEG39 P65 (Input mode) Port CM PCM0/WAIT/SEG32...
Page 530: Figure 16-1: Type A Block Diagram
Chapter 16 Port Functions Port block diagrams Figure 16-1: Type A Block Diagram Internal bus WR PMCNn PMCNn WR PMNn PMNn Fnc. WR PNn Data I/O control Address RD PNn Remark: N = 1 to 5 : Port number n = 0 to 7 : Port pin for port number 0 and 1 n = 0 to 5 : Port pin for port number 2 to 5.
Page 531: Figure 16-2: Type B Block Diagram
Chapter 16 Port Functions Figure 16-2: Type B Block Diagram Internal bus WR PM6 PMC6n WR PM6 PM6n Fnc. WRP6 Address LCD Segment enable Segment drive signal RD P6 Remark: n = 0 to 5 Preliminary User’s Manual U14913EE1V0UM00...
Page 532: Figure 16-3: Type C Block Diagram
Chapter 16 Port Functions Figure 16-3: Type C Block Diagram Internal bus WR PMCAL PMCALn WR PMAL PMALn PALn WRPAL PALn Address LCD Segment enable Segment drive signal RD PAL Remark: n = 0 to 15 Preliminary User’s Manual U14913EE1V0UM00...
Page 533: Figure 16-4: Type D Block Diagram
Chapter 16 Port Functions Figure 16-4: Type D Block Diagram Internal bus WR PMCDL PMCDLn WR PMDL PMDLn WR PDL PDLn PDLn Data I /O control Address RD PDL Remark: n = 0 to 15 Preliminary User’s Manual U14913EE1V0UM00...
Page 534: Figure 16-5: Type E Block Diagram
Chapter 16 Port Functions Figure 16-5: Type E Block Diagram Internal bus WR PMCCS PMCCSn WR PMCS PMCSn _CS2,_CS3,_CS4 PCSn PCSn WRPCS LCD Segment enable Segment drive signal RD PCS Remark: n = 2, 3, 4 Preliminary User’s Manual U14913EE1V0UM00...
Page 535: Figure 16-6: Type F Block Diagram
Chapter 16 Port Functions Figure 16-6: Type F Block Diagram Internal bus WR PMCCT PMCCTn WR PMCT PMCTn _LWR,_UWR,_RD PCTn PCTn WRPCT Address LCD Segment enable Segment drive signal RD PCT Remark: n = 0 to 4 Preliminary User’s Manual U14913EE1V0UM00...
Page 536: Figure 16-7: Type G Block Diagram
Chapter 16 Port Functions Figure 16-7: Type G Block Diagram Internal bus WR PMCCM0 PMCCM0 WR PMCM0 PMCM0 PCM0 PCM0 WRPCM0 Address WAIT RD PCM0 LCD Segment enable Segment drive signal Preliminary User’s Manual U14913EE1V0UM00...
Page 537: Figure 16-8: Type H Block Diagram
Chapter 16 Port Functions Figure 16-8: Type H Block Diagram Internal bus WR PMCCM1 PMCCM1 WR PMCM1 PMCM1 CLKOUT PCM1 PCM1 WRPCM1 Address LCD Segment enable Segment drive signal RD PCM1 Preliminary User’s Manual U14913EE1V0UM00...
Page 538: Pin Functions Of Each Port
Chapter 16 Port Functions 16.3 Pin Functions of Each Port 16.3.1 Port 1 Port 1 is a 8-bit input/output port in which input or output can be specified in 1-bit units. Figure 16-9: Port 1 (P1) Address At Reset FFFFF400H Bit position Bit name Function...
Page 539: Figure 16-11: Port 1 Mode Control Register (Pmc1)
Chapter 16 Port Functions (b) Port 1 mode control register (PMC1) This register can be read or written in 8- or 1-bit units. Figure 16-11: Port 1 Mode Control Register (PMC1) Address At Reset PMC1 PMC17 PMC16 PMC15 PMC14 PMC13 PMC12 PMC11 PMC10 FFFFF44CH Bit Position Bit Name...
Page 540: Port 2
Chapter 16 Port Functions 16.3.2 Port 2 Port 2 is a 8-bit input/output port in which input or output can be specified in 1-bit units. Figure 16-12: Port 2 (P2) Address At Reset FFFFF402H Bit position Bit name Function 7 to 0 Input/output port (n = 7 to 0) Besides functioning as a port, in control mode, it also can operate as the serial interface (CSI0, CSI1,...
Page 541: Figure 16-14: Port 2 Mode Control Register (Pmc2)
Chapter 16 Port Functions (b) Port 2 mode control register (PMC2) This register can be read or written in 8- or 1-bit units. Figure 16-14: Port 2 Mode Control Register (PMC2) Address At Reset PMC2 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 FFFFF442H Bit Position Bit Name...
Page 542: Port 3
Chapter 16 Port Functions 16.3.3 Port 3 Port 3 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Figure 16-15: Port 3 (P3) Address At Reset FFFFF404H Bit position Bit name Function 5 to 0 Input/output port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as the real-time pulse unit (RPU)
Page 543: Figure 16-17: Port 3 Mode Control Register (Pmc3)
Chapter 16 Port Functions (b) Port 3 mode control register (PMC3) This register can be read or written in 8- or 1-bit units. Figure 16-17: Port 3 Mode Control Register (PMC3) Address At Reset PMC3 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF444H Bit Position Bit Name...
Page 544: Port 4
Chapter 16 Port Functions 16.3.4 Port 4 Port 4 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Figure 16-18: Port 4 (P4) Address At Reset FFFFF406H Bit position Bit name Function 5 to 0 Input/output port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as the real-time pulse unit (RPU)
Page 545: Figure 16-20: Port 4 Mode Control Register (Pmc4)
Chapter 16 Port Functions (b) Port 4 mode control register (PMC4) This register can be read or written in 8- or 1-bit units. Figure 16-20: Port 4 Mode Control Register (PMC4) Address At Reset PMC4 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 FFFFF446H Bit Position Bit Name...
Page 546: Port 5
Chapter 16 Port Functions 16.3.5 Port 5 Port 5 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Figure 16-21: Port 5 (P5) Address At Reset FFFFF408H Bit position Bit name Function 5 to 0 Input/output port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as the real-time pulse unit (RPU)
Page 547: Figure 16-23: Port 5 Mode Control Register (Pmc5)
Chapter 16 Port Functions (b) Port 5 mode control register (PMC5) This register can be read or written in 8- or 1-bit units. Figure 16-23: Port 5 Mode Control Register (PMC5) Address At Reset PMC5 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 FFFFF448H Bit Position Bit Name...
Page 548: Port 6
Chapter 16 Port Functions 16.3.6 Port 6 Port 6 is a 6-bit input/output port in which input or output can be specified in 1-bit units. Figure 16-24: Port 6 (P6) Address At Reset FFFFF40AH Bit position Bit name Function 5 to 0 Input/output port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as segment signal output of LCD...
Page 549: Figure 16-26: Port 6 Mode Control Register (Pmc6)
Chapter 16 Port Functions (b) Port 6 mode control register (PMC6) This register can be read or written in 8- or 1-bit units. Figure 16-26: Port 6 Mode Control Register (PMC6) Address At Reset PMC6 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 FFFFF44AH Bit Position Bit Name...
Page 550: Port Al
Chapter 16 Port Functions 16.4 Port AL Port AL is a 16-/8-bit input/output port that can be set the input or output mode in 1-bit units. Figure 16-27: Port AL (PAL) Address Reset PAL PAL15 PAL14 PAL13 PAL12 PAL11 PAL10 PAL9 PAL8 PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0 FFFFF000H 0000H Bit position Bit name Function...
Page 551: Port Ah
Chapter 16 Port Functions 16.5 Port AH Port AH is a 16-bit input/output port for which input/output can be specified bitwise. Figure 16-30: Port AH (PAH) Address Reset PAH7 PAH6 PAH5 PAH4 PAH3 PAH2 PAH1 PAH0 FFFFF002H 00H Bit position Bit name Function 7 to 0...
Page 552: Figure 16-32: Port Ah Mode Control Register (Pmcah)
Chapter 16 Port Functions (b) Port Mode Control Register AH (PMCAH) PMCAH can be read/written from/to in 16-bit units or bitwise. Figure 16-32: Port AH Mode Control Register (PMCAH) Address Reset PMCAH PMCAH7 PMCAH6 PMCAH5 PMCAH4 PMCAH3 PMCAH2 PMCAH1 PMCAH0 FFFFF042H 00H Bit Position Bit Name Function...
Page 553: Port Dl
Chapter 16 Port Functions 16.6 Port DL Port DL is a 16-bit input/output port in which input or output can be specified in 1-bit units. When using the higher 8 bits of PDL as PDLH and the lower 8 bits as PDLL, it can be used as an 8-bit input/output port that can specify input/output in 1-bit units.
Page 554: Figure 16-35: Port Dl Mode Control Register (Pmcdl)
Chapter 16 Port Functions (b) Port DL mode control register (PMCDL) The PMCDL register can be read or written in 16-bit units. When using the higher 8 bits of the PMCDL register as the PMCDLH register and the lower 8 bits as the PMCDLL register, it can be read or written in 8- or 1-bit units.
Page 555: Port Cs
Chapter 16 Port Functions 16.7 Port CS Port CS is a 3-bit input/output port in which input or output can be specified in 1-bit units. Figure 16-36: Port CS (PCS) Address At Reset PCS4 PCS3 PCS2 FFFFF008H Bit Position Bit Name Function 7 to 0 PCSn...
Page 556: Figure 16-38: Port Cs Mode Control Register (Pmccs)
Chapter 16 Port Functions (b) Port CS mode control register (PMCCS) This register can be read or written in 8- or 1-bit units. Figure 16-38: Port CS Mode Control Register (PMCCS) Address At Reset PMCCS PMCCS4 PMCCS3 PMCCS2 FFFFF048H Bit Position Bit Name Function 7 to 0...
Page 557: Port Ct
Chapter 16 Port Functions 16.8 Port CT Port CT is an 8-bit input/output port in which input or output can be specified in 1-bit units. Figure 16-39: Port CT (PCT) Address At Reset PCT4 PCT3 PCT2 PCT1 PCT0 FFFFF00AH Bit Position Bit Name Function 7 to 0...
Page 558: Figure 16-41: Port Ct Mode Control Register (Pmcct)
Chapter 16 Port Functions (b) Port CT mode control register (PMCCT) This register can be read or written in 8- or 1-bit units. Figure 16-41: Port CT Mode Control Register (PMCCT) Address At Reset PMCCT PMCCT4 PMCCT3 PMCCT2 PMCCT1 PMCCT0 FFFFF04AH Bit Position Bit Name...
Page 559: Port Cm
Chapter 16 Port Functions 16.9 Port CM Port CM is a 2-bit input/output port in which input or output can be specified in 1-bit units. Figure 16-42: Port CM (PCM) Address At Reset PCM1 PCM0 FFFFF00CH Bit Position Bit Name Function 1, 0 PCMn...
Page 560: Figure 16-44: Port Cm Mode Control Register (Pmccm)
Chapter 16 Port Functions (b) Port CM mode control register (PMCCM) This register can be read or written in 8- or 1-bit units. Figure 16-44: Port CM Mode Control Register (PMCCM) Address At Reset PMCCM PMCCM1 PMCCM0 FFFFF04CH Bit Position Bit Name Function PMCCM1...
Page 561: Chapter 17 Reset Function
Chapter 17 RESET Function When a low level is input to the RESET pin, there is a system reset and each hardware item of the V850E/CA1 / ATOMIC is initialized to its initial status. When the RESET pin changes from low level to high level, reset status is released and the CPU starts program execution.
Page 562: Figure 17-1: Reset Signal Acknowledgment
Chapter 17 RESET Function Reset signal acknowledgment Figure 17-1: Reset signal acknowledgment RESET Analog Analog Analog delay delay delay Elimination as noise Internal system Note reset signal Reset acknowledgment Reset release Note: The internal system reset signal continues in active status for a period of at least 4 system clocks after the timing of a reset release by the RESET signal.
Page 563: Initialization
Chapter 17 RESET Function 17.3 Initialization Initialize the contents of each register as needed within a program. Table 17-2 shows the initial values of the CPU, internal RAM, and on-chip peripheral I/O’s after reset. Table 17-2: Initial Values of CPU and Internal RAM After Reset On-Chip Hardware Register Name Initial Value...
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Page 565: Chapter 18 Voltage Regulator
Chapter 18 Voltage Regulator 18.1 Outline The V850E/CA1 incorporates two regulators to realize a 5-V single power supply, low power consump- tion, and to reduce noise. These regulators supply a voltage obtained by stepping down V power supply voltage to oscillation blocks and on chip logic circuits (excluding the A/D converter and output buffers).
Page 566 [MEMO] Preliminary User’s Manual U14913EE1V0UM00...
Page 567: Chapter 19 Internal Voltage Comparator
Chapter 19 Internal Voltage Comparator 19.1 Features • Input voltage comparison by comparator • The comparator compares an internal reference voltage with an input voltage at the comparator input pin VCMPIN. The comparison result can be read in interrupt status flag. •...
Page 568: Voltage Comparator Functions
Chapter 19 Internal Voltage Comparator 19.2 Voltage Comparator Functions The V850E/CA1 / ATOMIC device is designed to operate in a wide range of power supply from 3.5 V to 5.5 V. The conditions with respect to the operating voltages V conforms to the following specifi- cation: Table 19-1: Power Supply Voltage Operating Modes...
Page 569: Figure 19-2: Internal Voltage Comparator
Chapter 19 Internal Voltage Comparator The comparator threshold and hysteresis are set by three external resistors: Figure 19-2: Internal Voltage Comparator hysteresis VCMPOUT measure point VCMPIN Status-Register Flag- ATOMIC Ref. The threshold has to be set to a voltage above 4.5 V to guarantee the frequency change within the time the supply voltage drops below 4.5 V.
Page 570: Internal Voltage Comparator Control Register (Vcmpm)
Chapter 19 Internal Voltage Comparator 19.2.1 Internal voltage comparator control register (VCMPM) The VCMPN0 register is an 8-bit register, which defines the operation mode of internal voltage compa- rator. This register can be read/ written in 8- or 1-bit units. Address At Reset VCMPM...
Page 571: Chapter 20 Flash Memory (Μpd70F3123)
Chapter 20 Flash Memory (µPD70F3123) The µPD70F3123 is the flash memory version of V850E/CA1 / ATOMIC, and is provided with a 256 KB flash memory. An instruction fetch from the flash memory takes one clock. The flash memory can be programmed using a dedicated flash writer. Furthermore this product has a Selfprogramming mode, which allows to program the flash memory by control of the application without any dedicated writer.
Page 572: Writing By Flash Writer
Chapter 20 Flash Memory (µPD70F3123) 20.2 Writing by Flash writer Writing can be performed either on-board or off-board by the dedicated flash writer. On-board programming The contents of the flash memory is rewritten after µPD70F3123 is mounted on the target system. It has to be ensured that the signals required for programming are made available to the flash writer.
Page 573: Communication System
Chapter 20 Flash Memory (µPD70F3123) 20.4 Communication System The communication between the dedicated flash writer and the µPD70F3123 is performed by serial communication using CSI. Transfer rate: up to 1.0 Mbps (MSB first) Figure 20-2: Flash Writer Communication via CSI0 DD5n SS5n SS3m...
Page 574: Flash Programming Circuitry
Chapter 20 Flash Memory (µPD70F3123) 20.5 Flash Programming Circuitry The following schematic shows the minimal circuitry, that is needed for the µPD70F3123. The circuitry incorporates a low-dropout voltage regulator (µPC29S78) as well as flash writer support. If the device is not used for Selfprogramming the V pins have to be connected via a pull down resistor to ground and the voltage regulator (µPC29S78) can be removed.
Page 575: Pin Handling
Chapter 20 Flash Memory (µPD70F3123) 20.6 Pin Handling When performing on-board writing, all required signals on the target system have to be made accessi- ble to the dedicated flash writer. Also, it has to be ensured that the modes are set correctly and the signal, which is required to enter the programming mode can be controlled by the flash writer.
Page 576: Serial Interface Pins
Chapter 20 Flash Memory (µPD70F3123) 20.6.2 Serial interface pins The following shows the pins used by the serial interface. Serial Interface Pins Used CSI0 SO0,SI0,SCK0 When connecting a dedicated flash writer to a serial interface pin, which is connected to other devices on-board, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc.
Page 577: Figure 20-6: Malfunction Of Other Input Pins
Chapter 20 Flash Memory (µPD70F3123) Malfunction of the other device When connecting a dedicated flash writer (output or input) to a serial interface pin (input or output) connected to another device (input), the signal output to the other device may cause the device to malfunction.
Page 578: Reset Pin
Chapter 20 Flash Memory (µPD70F3123) 20.6.3 RESET pin When connecting the reset signals of the dedicated flash writer to the RESET pin which is connected to the reset signal generation circuit on-board, conflict of signals may happen. To avoid the conflict of sig- nals, isolate the connection to the reset signal generation circuit.
Page 579: Programming Method
Chapter 20 Flash Memory (µPD70F3123) 20.7 Programming Method 20.7.1 Flash memory control To manipulate the flash memory the µPD70F3123 has to operate in a special flash memory program- ming mode. This mode can be entered either by applying the programming voltage of 7.8 V to the V before the reset is release or by entering the Selfprogramming mode.
Page 580: Selfprogramming Mode
Chapter 20 Flash Memory (µPD70F3123) 20.8 Selfprogramming Mode The flash Selfprogramming feature allows user to reprogram the flash contents by a user application program, without the necessity of an external flash writer. This feature allows an update of the application with only on-board resources and a user defined com- munication interface.
Page 581: Secure Selfprogramming
Chapter 20 Flash Memory (µPD70F3123) 20.9 Secure Selfprogramming 20.9.1 General description A flash memory area can only be erased as a whole. If parts of the lower flash area have to be updated, the complete flash memory has to be erased. This bears the risk that a problem during Selfprogram- ming, particularly a power failure, leaves the device without any valid program for start-up.
Page 582: Figure 20-10: Secure Selfprogramming Flow (1/2)
Chapter 20 Flash Memory (µPD70F3123) Figure 20-10: Secure Selfprogramming Flow (1/2) Area 1 Area 1 Area 1 0003FFFFH Bootprogram Upper Application Part 2 Erased Area Bootblock Size Signature Vector Table 00020000H Application Part 1 Application Part 1 Application Part 1 Bootprogram Bootprogram Bootprogram...
Page 583: Advantages Of Secure Selfprogramming
Chapter 20 Flash Memory (µPD70F3123) Figure 20-10: Secure Selfprogramming Flow (2/2) Area 0 Area 0 Area 0 0003FFFFH Application Part 1 Bootprogram New Application Upper Erased Part 2 Area Bootblock Size Vector Table 00020000H New Application Erased Erased Part 1 Bootprogram Bootprogram Bootprogram...
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Page 585: Appendix A Instruction Set List
Appendix A Instruction Set List A.1 Convention (a) Register symbols used to describe operands Register Symbol Explanation reg1 General registers: Used as source registers reg2 General registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General registers: Used mainly to store the remainders of division results and the higher order 3 bits of multiplication results.
Page 586 Appendix A Instruction Set List (c) Register symbols used in operation Register Symbol Explanation ¨ Input for GR [ ] General register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 587 Appendix A Instruction Set List (e) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (f) Condition codes Condition Name Condition Code Condition Formula Explanation (cond)
Page 588 Appendix A Instruction Set List A.2 Instruction Set (In Alphabetical Order) (1/4) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 rrrrr001110RRRRR GR[reg2]←GR[reg2] + GR[reg1] × × × × imm5,reg2 rrrrr010010iiiii GR[reg2]←GR[reg2] + sign-extend(imm5) ×...
Page 589 Appendix A Instruction Set List (2/4) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT HALT Stop 0000011111100000 0000000100100000 × × × reg2,reg3 GR[reg3]←GR[reg2](15 : 0) ll GR[reg2] (31 : 16) rrrrr11111100000 wwwww01101000100 JARL disp22,reg2 GR[reg2]←PC + 4 rrrrr11110dddddd PC←PC + sign-extend(disp22) ddddddddddddddd0...
Page 590 Appendix A Instruction Set List (3/4) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT PREPARE list12,imm5 Store-memory(sp – 4,GR[reg in list12],Word) 0000011110iiiiiL sp←sp – 4 Note Note Note LLLLLLLLLLL00001 repeat 1 step above until all regs in list12 are stored sp←sp –...
Page 591 Appendix A Instruction Set List (4/4) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT ST.W reg2,disp16[reg1] rrrrr111011RRRRR adr←GR[reg1] + sign-extend(disp16) Store-memory (adr,GR[reg2], Word) ddddddddddddddd1 Note 8 STSR regID,reg2 GR[reg2]←SR[regID] rrrrr111111RRRRR 0000000001000000 × × × × reg1,reg2 rrrrr001101RRRRR GR[reg2]←GR[reg2]–GR[reg1] ×...
Page 592 Appendix A Instruction Set List 16. ff = 00: Load sp in ep. 10: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18.
Page 593: Appendix B Index
Appendix B Index A/D conversion result registers 0 to 11 ..........497 A/D converter operation A/D trigger mode .
Page 594 Appendix B Index CKSR0 to CKSR2 ............. . . 331 Clock control register .
Page 595 Appendix B Index Bus states ..............176 Channel priorities .
Page 596 Appendix B Index ELISA status register ............. 483 ELISA temporary buffer registers .
Page 597 Appendix B Index Multiple interrupt processing control ..........220 NMI .
Page 598 Appendix B Index Port DL ..............42, 553 Port functions .
Page 599 Appendix B Index TEP1 ............... . . 480 TEP3 .
Page 600 Appendix B Index Watchdog timer Operation ..............307 WDTM .
Page 601 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

NEC V850E/CA1 ATOMIC Preliminary User's Manual

Chapter 1 Introduction

General

Device Features

Application Fields

Ordering Information

Pin Configuration (Top View)

Configuration of Function Block

Chapter 2 Pin Functions

List of Pin Functions

Description of Pin Functions

Types of Pin I/O Circuit and Connection of Unused Pin

Chapter 3 CPU Function

Features

CPU Register Set

Operation Modes

Address Space

Specific Registers

Chapter 4 Bus Control Function

Features

Bus Control Pins

Memory Block Function

Bus Cycle Type Control Function

Bus Access

Wait Function

Idle State Insertion Function

Bus Priority Order

Boundary Operation Conditions

Chapter 5 Memory Access Control Function

SRAM, External ROM, External I/O Interface

Page ROM Controller (ROMC)

Chapter 6 DMA Functions (DMA Controller)

Features

Configuration

Control Registers

DMA Bus States

Transfer Mode

Transfer Types

Transfer Object

DMA Channel Priorities

Next Address Setting Function

DMA Transfer Start Factors

Forcible Interruption

DMA Transfer End

Forcible Termination

Precautions

Chapter 7 Interrupt/Exception Processing Function

Features

Non-Maskable Interrupts

Maskable Interrupts

Noise Elimination Circuit

Software Exception

Exception Trap

Multiple Interrupt Processing Control

Interrupt Response Time

Periods in Which Interrupts Are Not Acknowledged

Chapter 8 Clock Generator

Features

Configuration

Main System Clock Oscillator

Control Registers

Power Saving Functions

Register Description

Securing Oscillation Stabilization Time

Chapter 9 Timer / Counter (Real Time Pulse Unit)

Timer D

Timer E

Quick Links

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Summary of Contents for NEC V850E/CA1 ATOMIC