NEC V850ES/F 3-L Series User Manual page 206

Chapter 4
Table 4-32
Releasing Source
Non-maskable interrupt request
signal
Maskable interrupt request signal
MainOSC
wavefrom
Main clock
STOP mode
status
Interrupt
request
Figure 4-8
206
The STOP mode is released by a non-maskable interrupt request signal or an
unmasked maskable interrupt request signal, regardless of the priority of the
interrupt request signal. If the STOP mode is set in an interrupt routine,
however, the operation is performed as follows:
• If an interrupt request signal with a priority lower than that the interrupt
request currently being serviced is generated, the STOP mode is released,
but the interrupt request with the lower priority is not acknowledged. The
interrupt request signal itself is held.
• If an interrupt request signal (including a non-maskable interrupt request
signal) with a priority higher than that of the interrupt request currently being
serviced is generated, the STOP mode is released, and this interrupt
request signal is acknowledged.
Operation after STOP mode is released by interrupt request signal
Interrupt Enabled (EI) Status
Execution branches to the handler address after the specified
oscillation stabilization time has elapsed.
Execution branches to the handler
address, or the next instruction is
executed after the oscillation
stabilization time has elapsed.
(b) Securing setup time after release of STOP mode
The main clock / 8MHz internal oscillator stop operating when the STOP mode
is set. Therefore, secure the oscillation stabilization time of the clock
oscillator(s) after releasing the STOP mode.
Releasing by non-maskable interrupt request signal or unmasked maskable
interrupt request signal:
• The setup time is secured by setting the OSTS register.
• When a source that releases the STOP mode occurs, an internal dedicated
timer starts counting in accordance with the setting of the OSTS register.
When this counter overflows, the normal operation mode is restored.
STOP mode
STOP mode timing for main clock operation
User's Manual U18743EE1V2UM00
Interrupt Disabled (DI) Status
The next instruction is executed
after the oscillation stabilization
time has elapsed.
OSC start OSC setup time
Clock Generator