Baud Rate Generator - NEC V850ES/F 3-L Series User Manual

Asynchronous Serial Interface (UARTD)

15.6 Baud Rate Generator

(1)
Figure 15-11
The dedicated baud rate generator consists of a source clock selector block
and an 8-bit programmable counter, and generates a serial clock during
transmission and reception with UARTDn. Regarding the serial clock, a
dedicated baud rate generator output can be selected for each channel.
There is an 8-bit counter for transmission and another one for reception.
Baud rate generator configuration
UDnPWR
f or f
XP1 XP2
f /2
XP1
f /4
XP1
Selector
. . .
f /1024
XP1
ASCKD0 Note
UDnCTL1:
UDnCKS3 to UDnCKS0
Note: External clock ASCKD0 is only availabel for UARTD0
Configuration of baud rate generator
(a) Base clock
When the UDnCTL0.UDnPWR bit is 1, the clock selected by the
UDnCTL1.UDnCKS[3:0] bits are supplied to the 8-bit counter. This clock is
called the base clock. When the UDnPWR bit = 0, f
level.
(b) Serial clock generation
A serial clock can be generated by setting the UDnCTL1 register and the
UDnCTL2 register.
The base clock is selected by UDnCTL1.UDnCKS3 to
UDnCTL1.UDnCKS0 bits.
The frequency division value for the 8-bit counter can be set using the
UDnCTL2.UDnBRS[7:0] bits.
User's Manual U18743EE1V2UM00
UDnPWR, UDnTXEn bit (or UDnRXE bit)
8-bit counter
f
UCLK
Match detector
UDnCTL2:
UDnBRS7 to UDnBRS0
Chapter 15
1/2 Baud rate
is fixed to the low
UCLK
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