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16-Bit Timer/Event Counter AA
Figure 10-35
Initial settings for upper 16-bit Timer (TMAAn)
Free-running mode setting
•
(TAAnCTL1: TAAnMD[2:0] = 101B)
•
Set Capture operation
(TAAnOPT0: TAAnCCS[1:0] = 11B)
•
Set Cascade operation
(TAAnOPT1: TAAnCSE = 1)
Initial settings for lower 16-bit Timer (TMAAm)
•
Clock selection
(TAAmCTL0: TAAmCKS[2:0])
•
Free-running mode setting
(TAAmCTL1: TAAmMD[2:0] = 101B)
•
Set Capture operation
(TAAmOPT0: TAAmCCS[1:0] = 11B)
TIAAm0 and TIAAm1 edge detection
setting (TAAmIS[1:0] and TAAmIS[3:2])
Timer operation enable (TAAmCE = 1)
→
both timer (TMAAm, TMAAn) start
TIAAm1 edge detection, capture of
lower 16-bit counter value to TAAmCCR1
and upper 16-bit counter value to TAAnCCR1.
TIAAm0 edge detection, capture of
lower 16-bit counter value to TAAmCCR0
and upper 16-bit counter value to TAAnCCR0.
Lower 16-bit counter overflow
Upper 16-bit counter overflow
Basic Flow of 32-bit Capture Mode
User's Manual U18743EE1V2UM00
START
Chapter 10
INTTAAmCC1 output
INTTAAmCC0 output
INTTAAmOV output
INTTAAnOV output
365
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