Code Flash Memory Mapping - NEC V850ES/F 3-L Series User Manual

32-bit single-chip microcontroller

Table of Contents

Flash Memory

7.1.2 Code flash memory mapping

Block 47(2 KB)

Block 31 (2 KB)

Block 0 (2 KB)

The microcontroller's internal code flash memory area is divided into blocks of

2 KB respectively 4 KB blocks and can be programmed/erased in block units.

All or some of the blocks can also be erased at once.

Following figures list the block structures and address assignments for all

V850ES/Fx3-L devices with code flash memory.

Additional information comprise:

• Boot swap cluster size

Configurable size of boot cluster for secure self-programming, refer to

"Secure self-programming (boot cluster swapping)" on page 279.

• Interleave

Interleave configuration of the flash memory blocks.

• CPU branch latency

Number of additional CPU clock cycles during instruction fetches of non-

linear code. The CPU branch latency may be configurable by the LATENCY

control bit of the option byte at address 0000 007B

Block 63(2 KB)

Block 0 (2 KB)

Code flash memory configuration for V850ES/Fx3-L devices.

User's Manual U18743EE1V2UM00

Block 127 (2

Block 95(2 KB)

Block 0 (2 KB)

8/16/32/64 KB

Code flash size

Boot swap cluster sizes