Cpu Register Set - NEC V850ES/F 3-L Series User Manual

CPU System Functions

3.2 CPU Register Set

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r0 (Zero Register)
r1
(Reserved for Assembler)
r2 (Interrupt Stack Pointer)
r3 (Stack Pointer (SP))
r4 (Global Pointer (GP))
(Text Pointer (TP))
r5
r6
r7
r8
r9
r1 0
r1 1
r1 2
r1 3
r1 4
r1 5
r1 6
r1 7
r1 8
r1 9
r2 0
r2 1
r2 2
r2 3
r2 4
r2 5
r2 6
r2 7
r2 8
r2 9
(Element Pointer (EP))
r3 0
(Link Pointer (LP))
r3 1
Figure 3-2
There are two categories of registers:
• General purpose registers
• System registers
All registers are 32-bit registers. An overview is given in the figure below. For
details, refer to V850ES User's Manual Architecture.
CPU register set
Some registers are write protected. That means, writing to those registers is
protected by a special sequence of instructions. Refer to "Write Protected
Registers" on page 155 for more details.
User's Manual U18743EE1V2UM00
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EIPC (Status Saving Register during interrupt)
EIPSW (Status Saving Register during interrupt)
FEPC (Status Saving Register during NMI)
FEPSW (Status Saving Register during NMI)
ECR (Interrupt/Execution Source Register)
PSW (Program Status Word)
CTPC (Status Saving Register during CALLT execution)
CTPSW (Status Saving Register during CALLT execution)
DBPC (Status Saving Register during exception/debug trap)
DBPSW (Status Saving Register during exception/debug trap)
CTBP (CALLT Base Pointer)
PC (Program Counter)
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