NEC V850ES/F 3-L Series User Manual page 472

Chapter 17
(4)
After reset: 00H
IICCLn
Note
CLDn
0 The SCL0n pin was detected at low level.
1 The SCL0n pin was detected at high level.
Condition for clearing (CLDn = 0)
• When the SCL0n pin is at low level
• When the IICEn = 0 (operation stop)
• After reset
DADn
0 The SDA0n pin was detected at low level.
1 The SDA0n pin was detected at high level.
Condition for clearing (DADn = 0)
• When the SDA0n pin is at low level
• When the IICEn = 0 (operation stop)
• After reset
SMCn
0 Operation in standard mode.
1 Operation in fast-speed mode.
DFCn
0 Digital filter off.
Digital filter on.
1
The digital filter can be used only in fast-speed mode.
In fast-speed mode, the transfer clock does not vary regardless of the DFCn bit setting (on/off).
The digital filter is used to eliminate noise in fast-speed mode.
472
IICCLn - IICn clock select registers
The IICCLn registers set the transfer clock for the I
These registers can be read or written in 8-bit or 1-bit units. However, the
CLDn and DADn bits are read-only. The SMCn, CLn1, and CLn0 bits are set by
the combination of the IICXn.CLXn bit and the OCKSTHn, OCKSn[1:0] bits of
the OCKSn register (see "Transfer rate setting" on page 475).
Reset input clears these registers to 00
Note Address:
R/W
7 6 <5>
0 0 CLDn
Bits 4 to 7 of IICCLn are read-only bits.
Detection of SCL0n pin level (valid only when IICCn.IICEn = 1)
Detection of SDA0n pin level (valid only when IICEn = 1)
Operation mode switching
Digital filter operation control
User's Manual U18743EE1V2UM00
.
H
IICCL0 FFFFFD84
H
<4> 3
DADn SMCn
Condition for setting (CLDn = 1)
• When the SCL0n pin is at high level
Condition for setting (DAD0n = 1)
• When the SDA0n pin is at high level
2
I C Bus (IIC)
2
Cn bus.
2 1
DFCn CLn1 CLn0
0