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Introduction
1.3.1 Internal units
CPU
Bus Control Unit
ROM
RAM
Ports
Clock Generator
Clock Monitor
On-chip Debug
function
Interrupt Controller
Key Interrupt
Function
UARTD
CSIB
CAN Controller
A/D Converter
Timers/counters
Watch Timer
Watchdog Timer 2
1.3.2 Structure of the manual
The CPU can execute almost all instruction processing, such as address
calculation, arithmetic and logic operations, and data transfer, in one clock
under control of a five-stage pipeline.
Dedicated hardware units such as a multiplier and a 32-bit barrel shifter are
provided to speed up complicated instruction processing.
The Bus Control Unit (BCU) and Memory Controller (MEMC) control the
access to on-chip peripheral I/Os.
The ROM consists of an internal flash memory and consists of the code flash.
For the available sizes, refer to Table 1-1 on page 21.
For the available RAM sizes, refer to Table 1-1 on page 21.
General-purpose port functions and control pin functions are available.
The Clock Generator generates the system clocks. It has four independent
oscillators to ensure system operability if the main oscillator should fail and to
provide low-speed clocks in power-save modes.
The Clock Monitor monitors the main oscillator. In case of failure, it can switch
the system to a different oscillator.
An on-chip debug function that uses the N-Wire interface is provided.
The Interrupt Controller (INTC) processes non-maskable and maskable
interrupt requests from the on-chip peripheral hardware and external sources.
Eight levels of priorities can be specified for these interrupt requests, and
multiple servicing control can be performed on interrupt sources.
A key interrupt request signal can be generated by applying a falling edge to
key input pins on eight channels.
The UARTs provide 2-wire Asynchronous Serial Interfaces.
The Clocked Serial Interfaces are 3-wire variable-length serial interfaces.
The CAN Controller is a small-scale digital data transmission system that
transfers data between units.
This is a high-speed, high-resolution 10-bit A/D Converter with 24 analog input
pins. This converter is of successive approximation type.
Five 16-bit timers/event counters TAA and one 16-bit interval timer TMM are
provided.
The Watch Timer (WT) output forms the reference for the bookkeeping of
daytime and calendar.
The Watchdog Timer (WDT2) is used to detect a program loop and system
errors. When the Watchdog Timer overflows, it generates a non-maskable
interrupt request signal or a system reset signal.
This manual explains how to use the V850ES/Fx3-L microcontroller devices. It
provides comprehensive information about the building blocks, their features,
and how to set registers in order to enable or disable specific functions.
The manual provides individual chapters for the building blocks. These
chapters are organized according to the grouping in the diagram.
User's Manual U18743EE1V2UM00
Chapter 1
25
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