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Chapter 4
(2)
Access
Address
Initial Value
Table 4-15
Bit position
Bit name
1 to 0
PSM[1:0]
a)
Sub-IDLE mode is entered if the processor is in subclock mode (clocked by f
182
PSMR - Power save mode control register
The 8-bit PSMR register is used to specify one of the power save modes. The
setting becomes effective when the mode is entered by setting PSC.STP to 1.
This register can be read/written in 1-bit or 8-bit units.
FFFF F820
.
H
00
. The register is initialized by any reset.
H
7
6
5
0
0
0
R
R
R
PSMR register contents
Specification of operation in software stand-by mode:
PSM1
PSM0
0
0
0
1
1
0
1
1
Note: The PSM0 and PSM1 bits take effect after PSC.STP = 1.
For information on these modes, refer to "Power save modes description" on
page 196.
User's Manual U18743EE1V2UM00
4
3
2
0
0
0
R
R
R
Function
Power save mode
IDLE1 mode
STOP mode
IDLE2 mode or sub-IDLE mode
STOP mode
Clock Generator
1
0
PSM1
PSM0
R/W
R/W
a
or f
).
XT
RL
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