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Chapter 4
4.2.1 General Clock Generator registers
(1)
Access
Address
Initial Value
Table 4-4
Bit position
Bit name
0
CCLSF
a)
Subclock f
is either f
SC
Note
168
The general Clock Generator registers control and reflect the operation of the
Clock Generator.
CCLS - CPU operation clock status register
The CCLS register indicates the CPU operation clock status.
This register can be read in 1-bit or 8-bit units.
FFFF F82E
.
H
00
. The register is initialized by any reset.
H
7
6
5
0
0
0
R
R
R
CCLS register contents
CPU operating clock status:
0: Operates on main system clock f
1: Operates on 240 KHz internal oscillator f
or f
, depending on SUBCLK bit of option byte 007B
XT
RL
If the Watchdog Timer WDT2 overflows before the oscillation stabilization time
of the MainOSC has elapsed, this is judged as an abnormal oscillation of the
MainOSC f
. Thus the CPU system clock f
X
oscillator f
.
RL
User's Manual U18743EE1V2UM00
4
3
2
0
0
0
R
R
R
Function
or subclock f
XX
.
RL
VBCLK
Clock Generator
1
0
0
CCLSF
R
R
a
.
SC
.
H
is changed to internal
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