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Chapter 17
Clock Stretching
Note
Figure 17-3
478
Heavy capacitive load and the dimension of the external pull-up resistor on the
2
I
C bus pins may yield extended rise times of the rising edge of SCLn and
SDAn. Since the controller senses the level of the I
such situation and takes countermeasures by stretching the clock SCLn in
order to ensure proper high level time t
After the microcontroller releases the (open-drain) SCLn pin it waits until the
SCLn level exceeds the valid high level threshold V
SCLn to low level before the nominal high level time t
This mechanism is the same used, when a slow I
down SCLn to low level to initiate a wait state.
It is assumed that the rise time f
Figure 17-3 shows an example.
V
thH
SCL signal
effective SCL
clock
Clock Stretching of SCLn
The effective clock frequency appearing at the SCLn pin calculates to
f
= 1 / (T
SCL_eff
SCL_nom
With a nominal frequency of f
rise time of t
= 135 ns the effective frequency is f
r
User's Manual U18743EE1V2UM00
of SCLn.
SCLH
is much bigger than the fall time f
r
t
t
t
r
SCLH
SCLL
T
SCL_nom
T
SCL_eff
+ t
)
r
= 355.6 KHz (T
SCL_nom
2
I
C Bus (IIC)
2
C bus signals it recognizes
. Then it does not pull
thH
has elapsed.
SCLH_nom
2
C slave device is pulling
.
f
t
r
= 2.812 µs and a
SCL_nom
= 339.31 KHz.
eff
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