Operation - NEC V850ES/F 3-L Series User Manual

Interrupt Controller (INTC)

5.2.1 Operation

acknowledgement
CPU processing
Figure 5-3
If a non-maskable interrupt is generated, the CPU performs the following
processing, and transfers control to the handler routine:
1. Saves the restored PC to FEPC.
2. Saves the current PSW to FEPSW.
3. Writes exception code 0010H to the higher halfword (FECC) of ECR.
4. Sets the NP and ID bits of the PSW and clears the EP bit.
5. Sets the handler address corresponding to the non-maskable interrupt to
the PC, and transfers control.
The processing configuration of a non-maskable interrupt is shown in
Figure 5-3.
NMI input
INTC
Non-maskable interrupt
request
PSW.NP
FEPC
FEPSW
ECR.FECC ← Exception
PSW.NP
PSW.EP
PSW.ID
PC
Interrupt service
Processing configuration of non-maskable interrupt
User's Manual U18743EE1V2UM00
1
0
←
Restored PC
← PSW
code
← 1
← 0
← 1
← NMI-Handler
address
Interrupt request pending
Chapter 5
227