Restore - NEC V850ES/F 3-L Series User Manual

Chapter 5

5.2.2 Restore

(1)
1
Figure 5-4
Caution
Note
228
NMI
Execution is restored from the non-maskable interrupt (NMI) processing by the
RETI instruction.
When the RETI instruction is executed, the CPU performs the following
processing, and transfers control to the address of the restored PC.
1. Restores the values of the PC and the PSW from FEPC and FEPSW,
respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW
is 1.
2. Transfers control back to the address of the restored PC and PSW.
Figure 5-4 illustrates how the RETI instruction is processed.
RETI instruction
PSW.EP
0
PSW.NP
0
PC EIPC
PSW EIPSW
Original processing restored
RETI instruction processing
When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction
during non-maskable interrupt processing, in order to restore the PC and PSW
correctly during recovery by the RETI instruction, it is necessary to set
PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction
immediately before the RETI instruction.
The solid line indicates the CPU processing flow.
User's Manual U18743EE1V2UM00
Interrupt Controller (INTC)
1
PC FEPC
PSW FEPSW