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Chapter 17
Processing by master device
IICn
ACKDn
STDn
L
SPDn
L
WTIMn
H
ACKEn
H
MSTSn
H
L
STTn
L
SPTn
WRELn
INTIICn
TRCn
L
Receive
Transfer lines
8
9
SCL0n
D0
ACK
SDA0n
Processing by slave device
IICn
ACKDn
STDn
L
SPDn
L
WTIMn
H
H
ACKEn
MSTSn
L
STTn
L
SPTn
L
WRELn
L
INTIICn
TRCn
H
Transmit
Figure 17-23
Note
524
IICn ← FFH Note
Note
1
2
3
4
D7
D6
D5
D4
IICn ← data
Example of slave to master communication
(when 9-clock wait is selected for both master and slave) (2/3)
(b) data
To cancel master wait, write FFH to IICn or set WRELn.
User's Manual U18743EE1V2UM00
5
6
7
8
9
D3
D2
D1
D0
ACK
2
I
C Bus (IIC)
IICn ← FFH Note
Note
1
2
3
D7
D6
D5
IICn ← data
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