Addresses - NEC V850ES/F 3-L Series User Manual

Chapter 17
Caution

17.6.2 Addresses

SCL0n
SDA0n
INTIICn
Figure 17-7
Note
482
When the IICC0.IICE0 bit of the microcontroller is set to 1 while
communications with other devices are in progress, the start condition may be
detected depending on the status of the communication line. Be sure to set the
IICC0.IICE0 bit to 1 when the SCL00 and SDA00 lines are high level.
The 7 bits of data that follow the start condition are defined as an address.
An address is a 7-bit data segment that is output in order to select one of the
slave devices that are connected to the master device via the bus lines.
Therefore, each slave device connected via the bus lines must have a unique
address.
The slave devices include hardware that detects the start condition and checks
whether or not the 7-bit address data matches the data values stored in the
SVAn register. If the address data matches the values of the SVAn register, the
slave device is selected and communicates with the master device until the
master device transmits a start condition or stop condition.
1 2 3
AD6 AD5 AD4
Address
The interrupt request signal (INTIICn) is generated if a local address or
extension code is received during slave device operation.
The slave address and the eighth bit, which specifies the transfer direction as
described in "Transfer direction specification" on page 483, are written together
to IIC shift register n (IICn) and then output. Received addresses are written to
the IICn register.
The slave address is assigned to the higher 7 bits of the IICn register.
User's Manual U18743EE1V2UM00
4 5 6 7
AD3 AD2 AD1 AD0
Address
2
I C Bus (IIC)
8 9
R/W
Note