Compare Match Interrupt In Timer Trigger Mode; Timing That Makes The A/D Conversion Result Undefined - NEC V850E/IA1 mPD703116 User Manual

13.10.5 Compare match interrupt in timer trigger mode

A TM0n timer 0 register underflow interrupt (INTTM00 or INTTM01) and CM003 or CM013 interrupt (INTCM003 or
INTCM013) is an A/D conversion start trigger that starts conversion operation (n = 0, 1). At this time, the CM003 or
CM013 match interrupt (INTCM003 or INTCM013) also functions as a compare register match interrupt for the CPU.
In order not to generate these match interrupts for the CPU, disable interrupts using the mask bits (TM0MK0,
TM0MK1, CM03MK0, CM03MK1) of the interrupt control registers (TM0IC0, TM0IC1, CM03IC0, CM03IC1).

13.10.6 Timing that makes the A/D conversion result undefined

If the timing of the end of A/D conversion and the timing of the stop of operation of the A/D converter conflict, the
A/D conversion value may be undefined. Because of this, be sure to read the A/D conversion result while the A/D
converter is in operation. Furthermore, when reading an A/D conversion result after the A/D converter operation has
stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result read timing is shown in Figures 13-14 and 13-15 below.
Figure 13-14. Conversion Result Read Timing (When Conversion Result Is Undefined)
ADCRnm
INTADn
ADCEn
Remark n = 0, 1, m = 0 to 7
Figure 13-15. Conversion Result Read Timing (When Conversion Result Is Normal)
ADCRnm
INTADn
ADCEn
Remark n = 0, 1, m = 0 to 7
672
CHAPTER 13 A/D CONVERTER
A/D conversion end
Normal conversion result
Normal conversion
result read
A/D conversion end
A/D operation stopped
User's Manual U14492EJ3V0UD
A/D conversion end
Undefined value
A/D operation
stopped
Normal conversion result
Normal conversion
result read
Undefined
value read