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16-Bit Interval Timer M
(2)
Address: FFFF F690
Symbol
7
TM0CTL0
TM0CE
Caution
SELCNT0
a
register
SEL07 bit
TM0CKS2
X
X
X
X
0
1
X
X
X
a)
Refer to chapter "Clock Generator" on page 179 for details of SELCNT0 register.
Note
Caution
TM0CTL0 - TMM0 control register 0
The TM0CTL0 register is an 8-bit register that controls the operation of TMM.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00
H
6
5
4
0
0
0
Changing the TM0CTL0.TM0CKS[2:0] bits is prohibited while the timer is
operating (TM0CE = 1). Thus rewriting of these bits with the same value is
permitted.
The TM0CTL.TM0CE bit can be changed at any time.
TM0CE
Disable internal operating clock operation
0
(asynchronously reset TMM0).
1
Enable internal operating clock operation.
The TM0CE bit controls the internal operating clock and asynchronously reset of
TMM0. When this bit is cleared to 0, the internal operating clock of TMM is stopped,
and TMM0 is asynchronously reset.
When the TM0CE bit is set to 1, the internal operating clock is enabled within two
input clocks, and the timer counts up.
TM0CTL0 register
TM0CKS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
PRSI can be set by the option bytes:
Refer to "Flash Memory" on page 259 for details.
1.
Set TM0CKS2 to TM0CKS0 bits at TM0CE = 0. When the TM0CE bits is set
from 0 to 1, the TM0CKS2 to TM0CKS0 bits can be set at the same time.
2.
Set bit 6-3 to 0.
User's Manual U18743EE1V2UM00
H
.
3
2
0
TM0CKS2
TM0CKS1
Control of operation of timer M0
Selection of internal count clock
TM0CKS0
Input
0
f
XP1
1
f
/2
XP1
0
f
/4
XP1
1
f
/64
XP1
f
/512
XP1
0
1
0
1
Chapter 11
1
0
R/W
TM0CKS0
R/W
PRSI = 0
PRSI = 1
f
f
XX
f
/2
f
XX
f
/4
f
XX
f
/64
f
XX
XX
f
/512
f
/1024
XX
XX
f
/8
RH
INTWT
f
/8
RL
f
XT
After
reset
00
H
/2
XX
/4
XX
/8
XX
/128
373
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