Chapter 2
2.4.10 Port type D1O1-UI
WR
WR
WR
WR
WR
WR
WR
RD
1st alternate f unction
_DRST signal
(On-chip debug mode)
Figure 2-18
60
PU
PUmn
INTR
INTRmn
INTF
INTFmn
OCDM
OCDM0
PMC
PMCmn
PM
PMmn
PORT
Pmn
Address
Edge
Noise
detector
remov al
(f) On-chip debug
input control
Port type D1O1-UI block diagram
User's Manual U18743EE1V2UM00
(c) Pull-up control
(a) Output buffer control
(b) Input buffer control
(e) Alternate function input
control
(g) Pull-down c ontr ol
POCRES
Pin Functions
EVDD
Pch
Pmn
Nch