NEC V850ES/F 3-L Series User Manual page 218

Chapter 4
(2)
(3)
Main clock
Internal oscillator
clock
Internal reset
signal
Figure 4-11
(4)
218
Start and stop
The Clock Monitor operation must be enabled by setting bit CLM.CLME to 1.
Once this bit has been set, it cannot be cleared to 0 by any means other than
reset.
The Clock Monitor is automatically started as soon as the main oscillator is
stable, indicated by OSTC.MSTS = 1.
The Clock Monitor automatically stops under the following conditions:
• While oscillation stabilization time is being counted after STOP mode is
released
• When the main clock is stopped (PCC.MCK bit = 1 during subclock
operation, or PCC.CLS bit = 0 during main clock operation)
• When the sampling clock is stopped (240 KHz internal oscillator)
• When the CPU operates with 8 MHz internal oscillator
• When the CPU operates with 240 KHz internal oscillator
Operation when main clock oscillation is stopped (CLME bit = 1)
If oscillation of the main clock is stopped when the CLME bit = 1, an internal
reset signal is generated as shown in the following figure.
When oscillation of main clock is stopped
Operation in STOP mode or after STOP mode is released
If the STOP mode is set with the CLME bit = 1, the monitor operation is
stopped in the STOP mode and while the oscillation stabilization time is being
counted. After the oscillation stabilization time, the monitor operation is
automatically started.
User's Manual U18743EE1V2UM00
Four internal oscillator clocks
Clock Generator