NEC V850E/RS1 User Manual

32-/16-bit single-chip microcontroller with can interface

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User's Manual

V850E/RS1

32-/16-bit Single-Chip Microcontroller with CAN

Interface

Hardware

µPD70F3402, µPD70F3403, µPD70F3403A

Document No. U16702EE3V2UD00

Date Published April 2006

Printed in Germany

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Page 1 User’s Manual V850E/RS1 32-/16-bit Single-Chip Microcontroller with CAN Interface Hardware µPD70F3402, µPD70F3403, µPD70F3403A Document No. U16702EE3V2UD00 Date Published April 2006 © NEC Electronics Corporation 2006 Printed in Germany Downloaded from Elcodis.com electronic components distributor...
Page 2 All (other) product, brand, or trade names used in this pamphlet are the trademarks or registered trademarks of their respective owners. Product specifications are subject to change without notice. To ensure that you have the latest product data, please contact your local NEC Electronics sales office. User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com...
Page 3 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 4 Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd. Arcadiastrasse 10 District, Beijing 100083, P.R.China Santa Clara, CA 95050-2554, U.S.A.
Page 5: Preface
Preface Readers This User’s Document is intended for users who want to understand the func- tions of the V850E/RS1. Purpose This User’s Document presents the hardware manual of V850E/RS1. Organization This system specification describes the following sections: • Pin function •...
Page 6 User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 7: Table Of Contents
Table of Contents Preface ............5 Chapter 1 Introduction.
Page 8 Port Function Operation ..........169 4.4.1 Write to I/O ports.
Page 9 Bus Hold Function ........... . 223 5.7.1 Functional outline .
Page 10 Chapter 9 16-Bit Interval Timer M......... 355 Features .
Page 11 13.6 Interrupt Request Signals ..........442 13.7 Operation .
Page 12 Chapter 16 FCAN Controller ..........525 16.1 Overview .
Page 13 Chapter 17 Interrupt/Exception Processing Function ......685 17.1 Features ............685 17.2 Non-Maskable Interrupts .
Page 14 Chapter 20 Regulator........... . 747 20.1 Outline.
Page 15 Chapter 26 CRC Function ..........793 26.1 Functions .
Page 16 Appendix A Instruction Set List..........835 Appendix B Index .
Page 17 List of Tables Figure 1-1: Pin Configuration ......................33 Figure 1-2: Internal Block Diagram ....................35 Figure 2-1: Pin I/O Circuits ......................60 Figure 3-1: CPU Register Set ......................62 Figure 3-2: Program Counter (PC) Format ..................63 Figure 3-3: Interrupt Status Saving Registers (EIPC and EIPSW) Format ........
Page 18 Figure 4-23: Port Function Control Register 3 (PFC3) Format ............. 128 Figure 4-24: Port Function Control Expansion Register 3 (PFCE3) Format ......... 129 Figure 4-25: Pull-up Resistor Option Register 3 (PU3) Format ............ 130 Figure 4-26: Pull-down Resistor Option Register 3 (PD3) Format ..........130 Figure 4-27: External Interrupt Falling Edge Specification Register 3 (INTF3) Format ....
Page 19 Figure 4-81: Type W-SDW11 Block Diagram ................185 Figure 4-82: Type E-SD7 Block Diagram ..................186 Figure 4-83: Type A-1 Block Diagram ................... 187 Figure 4-84: Type U-SDW11E Block Diagram................188 Figure 4-85: Type G-SD7A Block Diagram..................189 Figure 4-86: Type G-SDW8E Block Diagram ................
Page 20 Figure 7-7: TMPn Dedicated I/O Control Register 0 (TPnIOC0) Format ........264 Figure 7-8: TMPn Dedicated I/O Control Register 1 (TPnIOC1) Format ........265 Figure 7-9: TMPn Dedicated I/O Control Register 2 (TPnIOC2) Format ........266 Figure 7-10: TMPn Option Register 0 (TPnOPT0) Format ............267 Figure 7-11: Selector Operation Control Register 0 (SELCNT0) Format ........
Page 21 Figure 8-23: Basic Operation Timing in External Trigger Pulse Output Mode ....... 333 Figure 8-24: Flowchart of Basic Operation in One-Shot Pulse Mode ..........335 Figure 8-25: Timing of Basic Operation in One-Shot Pulse Mode ..........336 Figure 8-26: Flowchart of Basic Operation in PWM Mode (1/2) ............ 338 Figure 8-27: Basic Operation Timing in PWM Mode (1/2) .............
Page 22 Figure 12-12: Timing of Continuous Transmission Operation ............419 Figure 12-13: UART Reception......................420 Figure 12-14: Receive Data Read Flow................... 421 Figure 12-15: Noise Filter Circuit ..................... 424 Figure 12-16: Configuration of Baud Rate Generator ..............425 Figure 12-17: Permissible Baud Rate Range for Reception ............428 Figure 12-18: Transfer Rate for Continuous Transmission..............
Page 23 Figure 14-26: Single Buffer Transfer Mode (Master, Receive Only) Timing ........492 Figure 14-27: Single Buffer Transfer Mode (Master, Transmit/Receive) Timing ......493 Figure 14-28: Single Buffer Transfer Mode (Slave, Transmit Only) Timing ........494 Figure 14-29: Single Buffer Transfer Mode (Slave, Receive Only) Timing ........495 Figure 14-30: Single Buffer Transfer Mode (Slave, Transmit/Receive) Timing .......
Page 24 Figure 16-29: CAN Module Last Error Information Register (CnLEC) Format ........ 600 Figure 16-30: CAN Module Information Register (CnINFO) Format ..........601 Figure 16-31: CAN Module Error Counter Register (CnERC) Format ..........602 Figure 16-32: CAN Module Interrupt Enable Register (CnIE) Format (1/2) ........603 Figure 16-33: CAN Module Interrupt Status Register (CnINTS) Format (1/2) .........
Page 25 Regulator Block Diagram ..................747 Figure 20-2: REGC Pin Connection (REGC = Capacity)............... 748 Figure 21-1: Address Assignment of Flash Blocks for V850E/RS1 ..........751 Figure 21-2: Environment Required for Writing Programs to Flash Memory ......... 752 Figure 21-3: Communication with Dedicated Flash Programmer (UARTA0)......... 753 Figure 21-4: Communication with Dedicated Flash Programmer (CSIB0) ........
Page 26 Timing Chart of Selecting Normal Operation Mode........... 773 Figure 22-5: Timing Chart of Selecting On-Chip Debug Mode ............773 Figure 22-6: Connection to N-Wire Emulator (NEC Electronics IE-V850E1-CD-NW: N-Wire Card) ......................774 Figure 22-7: Pin Configuration of Connector for Emulator Connection (Target System Side)..775 Figure 22-8: Example of Recommended Emulator Connection Circuit .........
Page 27 List of Tables Table 1-1: Product Versions ......................30 Table 1-2: Port Functions and Control Function ................38 Table 2-1: Pin of Power Supplies ....................39 Table 2-2: Port Pins ......................... 39 Table 2-3: Non-port pins ........................41 Table 2-4: Pin Operation States in Various Modes................
Page 28 Table 15-2: Transfer Targets ......................520 Table 15-3: Comparison of DMA Transfer Modes ................524 Table 16-1: Overview of Functions ....................526 Table 16-2: Frame Types ........................ 529 Table 16-3: RTR Frame Settings..................... 531 Table 16-4: Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits ......532 Table 16-5: Data Length Setting......................
Page 29: Chapter 1 Introduction
It is possible to program the user application directly on the target board, on which the V850E/RS1 is mounted. In such case, sys- tem development time can be reduced and system maintainability after shipping can be markedly improved.
Page 30: Features
Chapter 1 Introduction 1.2 Features • - core : V850E - Number of instructions : 83 - Minimum instruction execution time : 31.25 ns (during 32 MHz operations) for 3402 : 25 ns (during 40 MHz operations) for 3403 and 3403A : 32 bits ×...
Page 31 Chapter 1 Introduction : 2 channels × 32 message buffers Note • CAN (2.0B active) • A/D converter - 10-bit resolution : 16 inputs (with auto discharge function and diagnostic mode) • Interrupts : 60 vectored interrupts - Non-maskable interrupts : 2 sources (NMI, Watchdog) - Maskable interrupts : External: 8, Internal: 51 sources...
Page 32: Applications
Chapter 1 Introduction 1.3 Applications The V850E/RS1 is a device designed for car manufacturers. It is ideally suited for automotive applica- tions, like Safety System. It is also an excellent choice for other applications where a combination of sophisticated peripheral functions with CAN network support is required like Body Electronics Applica- tion.
Page 33: Pin Configuration (Top View)
Note Note PDL1/AD1 P10/INTP0 Note PDL0/AD0 P11/TIP31/TOP31 P12/TIP30/TOP30/ADTRG Note FLMD0 PCT6/ASTB Note PCT4/RD Note REGC0 PCT1/WR1 Note PCT0/WR0 Note PCM3/HLDRQ V850E/RS1 Note PCM2/HLDAK Note RESET PCM1/CLKOUT Note P00/SI31 PCM0/WAIT Note P01/SO31 PCS1/CS1 Note P02/SCK31 PCS0/CS0 P03/CS310 Note P915/TIP11/TOP11/INTP6/AD15 P04/CS311 Note...
Page 34 Chapter 1 Introduction Pin Identification Note Address/data bus Programmable clock output AD0 to AD15 ADTRG A/D trigger input PCM0 to PCM3 Port CM ANI0 to ANI15 Analog input PCT0, PCT1, Port CT ASCKA0 to ASCKA1 Asynchronous serial clock PCT4, PCT6 Note Address strobe PDL0 to PDL13...
Page 35: Configuration Of Function Block
Chapter 1 Introduction 1.6 Configuration of Function Block 1.6.1 Internal block diagram Figure 1-2: Internal Block Diagram Flash ROM INTC Note Instruction CS0, CS1 INTP0 to INTP7 128 KB/ queue Note AD0 to AD15 256 KB Note WR0, WR1 Timer 32-bit barrel Multiplier Note...
Page 36: On-Chip Units
Chapter 1 Introduction 1.6.2 On-chip units The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits or 32 bits × 32 bits →...
Page 37 (INTWDT) or a reset signal after an overflow occurs. (12) Serial interface The V850E/RS1 includes four kinds of serial interfaces: asynchronous serial interface A (UARTA), and 3-wire variable-length serial interface B (CSIB), 3 wire variable length serial interface 3 with transmit and receive buffer (CSI3) and maximum two-channel CAN are provided as serial inter- faces.
Page 38: Table 1-2: Port Functions And Control Function
Chapter 1 Introduction Table 1-2: Port Functions and Control Function Port Port Control Function Function 7-bit I/O Serial interface I/O, external interrupt 3-bit I/O External interrupt, Timer I/O 9-bit I/O External interrupt, serial interface I/O, timer I/O 3-bit I/O Serial interface I/O 6-bit I/O Timer I/O, Serial interface I/O General-...
Page 39: Chapter 2 Pin Functions
Chapter 2 Pin Functions 2.1 List of Pin Functions The names and functions of V850E/RS1 pins are described below. These pins can be divided into port pins and non-port pins according to their functions. Table 2-1 shows the relationship between power supplies and the pins below.
Page 40 Chapter 2 Pin Functions Table 2-2: Port Pins (2/2) Pin Name Function Alternate Function TIQ01/TOQ01 TIQ02/TOQ02 Port 5 TIQ03/TOQ03 6-bit I/O port TIQ00/TOQ00 Input/output can be specified in 1-bit units. SI30 SO30 Port 7 P70 to P715 16-bit I/O port ANI0 to ANI15 Input/output can be specified in 1-bit units.
Page 41: Table 2-3: Non-Port Pins
Chapter 2 Pin Functions Non-port pins Table 2-3: Non-port pins (1/3) Pin Name Function Alternate Function External interrupt (non-maskable, analog, Input – noise elimination) INTP0 INTP1 P37/TIP00/TOP00/(CS312) INTP2 P05/CS312 INTP3 P06/CS13 External interrupt request input (maskable, Input analog, noise elimination) INTP4 P913/TIP20/TOP20/PCL INTP5...
Page 42 Chapter 2 Pin Functions Table 2-3: Non-port pins (2/3) Pin Name Function Alternate Function TOQ00 Timer output (TMQ00) P53/TIQ00 TOQ01 Timer output (TMQ01) P50/TIQ01 TOQ02 Timer output (TMQ02) P51/TIQ02 TOQ03 Timer output (TMQ03) P52/TIQ03 Output TOQ10 Timer output (TMQ10) P93/CS302/TIQ10 TOQ11 Timer output (TMQ11) P90/SCK30/TIQ11...
Page 43 Chapter 2 Pin Functions Table 2-3: Non-port pins (3/3) Pin Name Function Alternate Function Reference voltage input for A/D converter Input – REF0 (same potential as V Ground potential for A/D converter (same – potential as V ADTRG Input A/D converter external trigger input P12/TIP30/TOP30 Input Debug data input...
Page 44: Pin States
Chapter 2 Pin Functions 2.2 Pin States The operation states of pins in various mode are described in Table 2-4. Table 2-4: Pin Operation States in Various Modes Halt Mode External Bus Idle Mode Idle State Bus Control Pin Reset During DMA Interface Bus Hold...
Page 45: Description Of Pin Functions
Chapter 2 Pin Functions 2.3 Description of Pin Functions P00 to P06 (Port 0) Port 0 is a 7-bit I/O port for which input and output can be specified in 1-bit units. In addition to I/O port pins, P00 to P06 can also be used as CS30, CSI31 and external interrupt request inputs.
Page 46 Chapter 2 Pin Functions P10, P11, P12 (Port 1) Port 1 is 3-bit I/O port for which input and output can be specified in 1-bit units. In addition to I/O pins, P10 to P12 can also be used as external interrupt request inputs, timer/ counter I/O in the control mode and the external A/D conversion start trigger.
Page 47 Chapter 2 Pin Functions P30 to P38 (Port 3) Port 3 is a 9-bit I/O port for which input and output can be set in 1-bit units. In addition to I/O port pins, P30 to P38 can also be used as external interrupt request inputs, serial interface I/O, CAN I/F I/O and timer/counter I/O in the control mode.
Page 48 Chapter 2 Pin Functions P40 to P42 (Port 4) … Bi-directional I/O Port 4 is a 3-bit I/O port for which input and output can be set in 1-bit units. In addition to I/O port pins, P40 to P42 can also be used as serial interface I/O in the control mode. The port/control mode can be selected for each bit.
Page 49 Chapter 2 Pin Functions P50 to P55 (Port 5) Port 5 is a 6-bit I/O port for which input and output can be set in 1-bit units. In addition to I/O port pins, P50 to P55 can also be used as timer/counter I/O and CSI3 in the con- trol mode.
Page 50 Chapter 2 Pin Functions P70 to P715 (Port 7) … Bi-directional I/O Port 7 is a 16-bit I/O port for which input and output can be set in 1-bit units. In addition to I/O port pins, P70 to P715 can also be used as analog output pins for the A/D con- verter in the control mode.
Page 51 Chapter 2 Pin Functions P90 to P915 (Port 9) … Bi-directional I/O Port 9 is a 16-bit I/O port for which input and output can be set in 1-bit units. In addition to I/O port pins, P90 to P915 can also be used as serial interface I/O, timer/counter I/O, external interrupt request inputs, clock output, and on chip debug function in the control mode.
Page 52 The address bus, data bus, and control bus are in high impedance while this signal is active. - HLDRQ (hold request) … Input This is an input pin by which an external device requests the V850E/RS1 to release the address bus, data bus, and control bus release requests. This pin accepts asynchronous input for CLKOUT.
Page 53 Chapter 2 Pin Functions PCS0, PCS1 (Port CS) … Bi-directional I/O Port CS is a 2-bit I/O port for which input and output can be set in 1-bit units. An on-chip pull-up and Pull-down resistor can be specified for use in 1-bit units using pull-up/ pull- down resistor option register CS (PUCS, PDCS).
Page 54 Chapter 2 Pin Functions (10) PCT0, PCT1, PCT4, PCT6 (Port CT) … Bi-directional I/O Port CT is a 4-bit I/O port for which input and output can be set in 1-bit units. In addition to I/O pins, PCT0, PCT1, PCT4, PCT6 can also be used as control signal output pins for external memory expansion in the control mode.
Page 55 Chapter 2 Pin Functions (11) PDL0 to PDL13 (port DL) … Bi-directional I/O Port DL is a 14-bit I/O port for which input and output can be set in 1-bit units. During flash memory programming (corresponding to input of high level to FLMD0), PDL5 func- tions as the FLMD1 pin.
Page 56 Chapter 2 Pin Functions (12) FLMD0(flash programming mode) Input This is the input pin that specifies the operation mode. Fix this pin to low level so that its level does not change during operation. The internal circuit samples the status of the FLMD0 pin at the rising edge of the RESET pin. In the normal operation mode, connect this pin to V (13) RESET (reset) …...
Page 57: Pin I/O Circuit Types, I/O Buffer Power Supply And Handling Of Unused Pins
Chapter 2 Pin Functions 2.4 Pin I/O Circuit Types, I/O Buffer Power Supply and Handling of Unused Pins Table 2-5: Pin I/O Circuit Types (1/3) Pin Name I/O Circuit Types Recommended Connection P00/SI31 P01/SO31 P02/SCK31 Connect it to V or V through independent resistor.
Page 58 Chapter 2 Pin Functions Table 2-5: Pin I/O Circuit Types (2/3) Pin Name I/O Circuit Types Recommended Connection P90/TIQ11/TOQ11/SCK30 5-AM P91/TIQ12/TOQ12/CS300 5-AM P92/TIQ13/TOQ13/CS301 5-AM P93/TIQ10/TOQ10/CS302 5-AM Connect it to V or V through independent resistor. P94/ASCKA1/CS303 5-AM P95/RXDA1/(SCK30) 5-AM P96/TXDA1/(CS300) 5-AM P97/SIB1/{DDI} 5-AM...
Page 59 Connect to V via a capacitor. Note 2 REGC1 Connect to V via a capacitor. Notes: 1. NEC specifies to connect 1µF to REGC0. 2. NEC specifies to connect 4.7 µF to REGC1. User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 60 Chapter 2 Pin Functions Figure 2-1: Pin I/O Circuits Type 5 Type 5-AE Data Pullup P-ch P-ch enable IN/OUT Output N-ch disable Data P-ch IN/OUT Input enable Output N-ch disable Input enable Type 2 Type 5-AM pull-up enable P-ch data P-ch IN/OUT output...
Page 61: Chapter 3 Cpu Function
Chapter 3 CPU Function The CPU of the V850E/RS1, which is based on RISC architecture, executes almost all instructions in one clock cycle due to its five-stage pipeline control. 3.1 Features • Number of instructions: • Minimum instruction execution time: 41.6 ns @ 24 MHz, 31.25 ns @ 32 MHz,...
Page 62: Cpu Register Set
Chapter 3 CPU Function 3.2 CPU Register Set The CPU registers of the V850E/RS1 can be classified into general purpose register set, which are used by programs, and system register set, which are used to control the execution environment. This chapter describe also specific registers which can be read or written using the LDSR and STSR instruc- tions.
Page 63: Program Register Set
Chapter 3 CPU Function 3.2.1 Program register set The program registers include general-purpose registers and a program counter. General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used.
Page 64: System Register Set
Chapter 3 CPU Function 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2: System Register Numbers Operand Specification Register...
Page 65 Chapter 3 CPU Function Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maska- ble interrupt occurs).
Page 66 Chapter 3 CPU Function NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW.
Page 67 Chapter 3 CPU Function Program status word (PSW) A program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of the LDSR instruction execution.
Page 68 Chapter 3 CPU Function Figure 3-6: Program Status Word (PSW) Format (2/2) Flag status Result of operation of Status of operation result saturation processing Maximum positive value is exceeded. 7FFFFFFFH Maximum negative value is exceeded. 80000000H Positive (maximum value is not exceeded) Holds value before Operation result itself operation Negative (maximum value is not exceeded)
Page 69 Chapter 3 CPU Function Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW. The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs.
Page 70: Special Registers
3.2.3 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850E/RS1 has the following special registers. • Power save control register (PSC) • Clock control register (CKC) • Main peripheral clock control register (MPCCTL) •...
Page 71 Chapter 3 CPU Function Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in <2> to the command register (PRCMD). <4>...
Page 72 Chapter 3 CPU Function Command register (PRCMD) The command register (PRCMD) is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register (power save control register (PSC)) is valid after data has been written in advance to the PRCMD register.
Page 73 Chapter 3 CPU Function System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Figure 3-11: System Status Register (SYS) Format Symbol Address After reset...
Page 74: Operation Modes
Chapter 3 CPU Function 3.3 Operation Modes 3.3.1 Operation modes The V850E/RS1 has the following operation modes. Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Page 75: Address Space
3.4 Address Space 3.4.1 CPU address space The CPU of the V850E/RS1 has 32-bit architecture and supports up to 4 GB of linear address space (data space) for operand addressing (data access). It also supports up to 64 MB of linear address space (program space) for instruction addressing.
Page 76: Image
Chapter 3 CPU Function 3.4.2 Image For instruction addressing, up to 16 MB of linear address space (program space) and an internal RAM area are supported. Up to 4 GB of linear address space (data space) is supported for operand address- ing (data access).
Page 77: Wrap-Around Of Cpu Address Space
Chapter 3 CPU Function 3.4.3 Wrap-around of CPU address space Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation.
Page 78: Memory Map
Chapter 3 CPU Function 3.4.4 Memory map The areas shown in Figure 3-16 are reserved in the V850E/RS1. Figure 3-16: Data Memory Map (Physical Addresses) 03FF FFFFH 03FF FFFFH Internal peripheral I/O area (4 KB) 03FF F000H (80 KB) 03FF EFFFH...
Page 79 Chapter 3 CPU Function Figure 3-17: Program Memory Map 03FF FFFFH Use prohibited (program fetch prohibited area) 03FF F000H 03FF EFFFH Internal RAM area (60 KB) 03FF 0000H Programmable peripheral 03FE FFFFH I/O area or use prohibited (program fetch prohibited area) 0100 0000H 00FF FFFFH External memory area...
Page 80 Chapter 3 CPU Function Figure 3-18: Memory Map Area for µPD70F3402, µPD70F3403 and µPD70F3403A µPD70F3402 µPD70F3403 and µPD70F3403A 03FF FFFFH 03FF FFFFH Internal peripheral Internal peripheral I/O area I/O area (4 KB) (4 KB) 03FF F000H 03FF F000H 03FF EFFFH 03FF EFFFH Internal RAM area Internal RAM area...
Page 81: Memory Areas
0000 0000H 0000 0000H (b) Interrupt/exception table The V850E/RS1 speeds up the interrupt response time by fixing handler addresses corresponding to interrupts/exceptions. A collection of these handler addresses is called an interrupt/exception table, which is mapped to the internal ROM area. When an interrupt/exception is acknowledged, execution jumps to a han- dler address and the program in the area starting from that address is executed.
Page 82 Chapter 3 CPU Function Internal RAM area 60 KB of addresses 3FF0000H to 3FFEFFFH are reserved as the internal RAM area. (a) µPD70F3402 10 KB are provided in the following addresses as physical internal RAM. • Addresses 3FFC800H to 3FFEFFFH Figure 3-20: Internal RAM Area (10 KB) 3FF EFFFH Internal RAM area (10 KB)
Page 83 Chapter 3 CPU Function Internal peripheral I/O area 4 KB of addresses 3FFF000H to 3FFFFFFH are allocated as the internal peripheral I/O area. Figure 3-22: Internal Peripheral I/O Area 3FF FFFFH Internal peripheral I/O area (4 KB) 3FF F000H Peripheral I/O registers that have functions to specify the operation mode for and monitor the sta- tus of the internal peripheral I/O are mapped to the internal peripheral I/O area.
Page 84: Recommended Use Of Address Space
Chapter 3 CPU Function 3.4.6 Recommended use of address space The architecture of the V850E/RS1 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
Page 85 Chapter 3 CPU Function Figure 3-24: Recommended Memory Map Program space Data space FFFF FFFFH Internal peripheral I/O FFFF F000H FFFF EFFFH Internal RAM xFFF FFFFH FFFF C000H Internal FFFF BFFFH peripheral I/O xFFF F000H xFFF EFFFH Internal RAM xFFF 7000H xFFF 6FFFH xFFE C000H 0400 0000H...
Page 86: Cautions
Three clocks are required to access an internal peripheral I/O register (without a wait cycle). The V850E/RS1 requires wait cycles according to the operating frequency. Set the following value to the VSWC register in accordance with the frequency used.
Page 87 Chapter 3 CPU Function (b) On-chip debug mode register (OCDM) This register is used to switch between the normal operation mode and the on-chip debug mode. The OCDM register is a special register (refer to 3.2.3 ”Special registers” on page 70). Writing is possible only using a specific sequence so that its contents cannot be rewritten by mistake in case of inadvertent program loops.
Page 88 Chapter 3 CPU Function Figure 3-27: Timing Chart When On-Chip Debug Function Is Not Used Reset release RESET Clearing of OCDM0 bit OCDM0 P911/{DRST} High-level I/O is possible Maintain low level after clearing of OCDM0 bit Figure 3-28: Timing Chart of Transition to Normal Operation Mode RESET (external reset input) (internal reset)
Page 89 Chapter 3 CPU Function Figure 3-29: Timing Chart of Transition to On-Chip Debug Mode To use on-chip debug mode by using power-on-clear function, input external reset longer than power-on-clear detection signal (internal reset) RESET (external reset input) OCDM0 bit is cleared to 00 (normal operation mode) by generation of power-on-clear detection signal (internal reset)
Page 90: Table 3-3: Access Conditions
Chapter 3 CPU Function Table 3-3: Access Conditions (1/2) Peripheral Register Name Access Function TPnCNT Read 1 or 2 • 1st access: No wait Write 16-bit timer/ • Continuous write: 3 or 4 TPnCCR0 event counter P Read 1 or 2 (TMP) (n = 0 to 4) •...
Page 91 Chapter 3 CPU Function Table 3-3: Access Conditions (2/2) Peripheral Register Name Access Function CnGMCTRL, CnGMCS, CnGMABT, CnGMABTD, Note + 1) × (1/(2 + j)) (MIN.) CnMASKaL, CnMASKaH, CANMODE Read/write CnCTRL, CnLEC, CnINFO, Note × 2 + 1) × (1/(2 + j)) (MAX.) CANMODE CnERC, CnIE, CnINTS, CnBRP, CnBTR, CnTS...
Page 92: Programmable I/O Area
Chapter 3 CPU Function 3.5 Programmable I/O Area The V850E/RS1 includes an additional memory area for the control of on-chip peripherals. The base address of this area is located in the external memory space. A control register setting is required to enable this additional memory.
Page 93: Peripheral I/O Registers
Chapter 3 CPU Function 3.6 Peripheral I/O Registers Table 3-4: Peripheral I/O Registers (1/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × FFFFF004H Port DL undefined × × FFFFF004H Port DLL PDLL undefined × × FFFFF005H Port DLH PDLH undefined ×...
Page 94 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (2/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × × FFFFF118H Interrupt control register PIC3 × × FFFFF11AH Interrupt control register PIC4 × × FFFFF11CH Interrupt control register PIC5 ×...
Page 95: Table 3-4: Peripheral I/O Registers
Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (3/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × × FFFFF168H Interrupt control register CB2RIC × × FFFFF16AH Interrupt control register CB2TIC × × FFFFF16CH Interrupt control register TQ1OVIC ×...
Page 96 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (4/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × FFFFF23EH A/D conversion result register 15 ADA0CR15 0000H × FFFFF240H A/D conversion result register DD ADA0CRDD 0000H × FFFFF242H A/D conversion result register SS ADA0CRSS 0000H...
Page 97 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (5/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × × FFFFF448H Port 4 mode control register PMC4 × × FFFFF44AH Port 5 mode control register PMC5 × FFFFF452H Port 9 mode control register PMC9 0000H...
Page 98 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (6/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × × FFFFF5A3H TMP1 timer-specific I/O control register 1 TP1IOC1 × × FFFFF5A4H TMP1 timer-specific I/O control register 2 TP1IOC2 ×...
Page 99 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (7/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × FFFFF6D1H Watchdog timer enable register WDTE × × FFFFF702H Port 1 function control expansion register PFCE1 × × FFFFF706H Port 3 function control expansion register PFCE3 ×...
Page 100 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (8/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × × FFFFFA10H UARTA1 control register 0 UA1CTL0 × FFFFFA11H UARTA1 control register 1 UA1CTL1 × FFFFFA12H UARTA1 control register 2 UA1CTL2 ×...
Page 101 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (9/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit External interrupt rising edge specification × × FFFFFC26H INTR3 register 3 External interrupt rising edge specification × × FFFFFC33H INTR9H register 9H ×...
Page 102 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (10/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × × FFFFFD41H CSI30 clock selection register CSIC0 × FFFFFD42H CSI30 receive data buffer SIRB0 0000H × FFFFFD42H CSI30 receive data buffer L SIRB0L ×...
Page 103 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (11/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × FFFFFE0CH MDMA ch0 destination address register DMDA0 × FFFFFE0CH MDMA ch0 destination address register L DMDA0L × FFFFFE0EH MDMA ch0 destination address register H DMDA0H ×...
Page 104 Chapter 3 CPU Function Table 3-4: Peripheral I/O Registers (12/12) Manipulatable bits Default Address Description Symbol value 1-bit 8-bit 16-bit × FFFFFE3CH MDMA ch4 destination address register DMDA4 × FFFFFE3CH MDMA ch4 destination address register L DMDA4L × FFFFFE3EH MDMA ch4 destination address register H DMDA4H ×...
Page 105: Chapter 4 Port Functions
• Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850E/RS1 features a total of 84 I/O ports consisting of the ports 0, 1, 3, 4, 5, 7, 9, CM, CS, CT, and DL. The port configuration is shown below.
Page 106: Table 4-1: I/O Buffer Power Supplies For Pins
Chapter 4 Port Functions Table 4-1: I/O Buffer Power Supplies for Pins Power Supply Corresponding Pin Port 7 REF0 Port CM, Port CS, port CT, port DL Port 0, Port 1, Port 3, Port 4, Port 5, Port 9, RESET, NMI Remark: NMI and RESET pins have no Port function.
Page 107: Port Configuration
Chapter 4 Port Functions 4.3 Port Configuration 4.3.1 Table of port configuration Table 4-2: Control Register Setting (1/4) Control Value Register Pin Name Other PFCE PSWAP 1 AV REF0 2 AV 3 NMI 4 P10/INTP0 INTP0 6 P11/TIP31/TOP31 TIP31 TOP31 P12/TIP30/TOP30/ TIP30 TOP30 ADTRG...
Page 108 Chapter 4 Port Functions Table 4-2: Control Register Setting (2/4) Control Value Register Pin Name Other PFCE PSWAP 29 P34/CRXD0 CRXD0 30 P35/CRXD1 CRXD1 31 P36/CTXD1 CTXD1 P37/TIP00/TOP00/ TIP00 CS312 TOP00 INTP1 INTP1/(CS312) 33 P38/TIP01/TOP01 TIP01 TOP01 34 V 35 REGC1 36 V 37 P50/TIQ01/TOQ01 TIQ01...
Page 109 Chapter 4 Port Functions Table 4-2: Control Register Setting (3/4) Control Value Register Pin Name Other PFCE PSWAP P915/TIP11/TOP11/ P915 INTP6 TOP11 TIP11 AD15 INTP6/AD15 59 PCS0/CS0 PCS0 CS0 60 PCS1/CS1 PCS1 CS1 61 PCM0/WAIT PCM0 WAIT 62 PCM1/CLKOUT PCM1 CLKOUT 63 PCM2/HLDAK PCM2 HLDAK 64 PCM3/HLDRQ...
Page 110: Table 4-3: Port Configuration
Chapter 4 Port Functions Table 4-2: Control Register Setting (4/4) Control Value Register Pin Name Other PFCE PSWAP 92 P78/ANI8 ANI8 93 P77/ANI7 ANI7 94 P76/ANI6 ANI6 95 P75/ANI5 ANI5 96 P74/ANI4 ANI4 97 P73/ANI3 ANI3 98 P72/ANI2 ANI2 99 P71/ANI1 ANI1 100 P70/ANI0 ANI0...
Page 111: Port Function Swap Control Register
Chapter 4 Port Functions 4.3.2 Port function swap control register This device has a special purpose register for swapping port function by setting control bit. The Swap function is implemented to allow flexible configuration. More detail of the settings by control bit is shown in Table 4-2, “Control Register Setting,” on page 107. This is an 8-bit register used to specify the input mode/output mode.
Page 112: Port 0
Chapter 4 Port Functions 4.3.3 Port 0 Port 0 is a 7-bit port for which I/O settings can be controlled in 1-bit units. Port 0 functions • 7bits I/O port • Port input/output specifiable in 1-bit units by port mode register 0 (PM0) •...
Page 113 Chapter 4 Port Functions (b) Port mode register 0 (PM0) This is an 8-bit register used to specify the input mode/output mode. This register can be read and written in 8-bit or 1-bit units. Figure 4-4: Port Mode Register 0 (PM0) Format Symbol Address After reset...
Page 114 Chapter 4 Port Functions Figure 4-5: Port Mode Control Register 0 (PMC0) Format (2/2) PMC03 P03 pin operation mode specification I/O port CS310 (Chip select0 output for CSI31) PMC02 P02 pin operation mode specification I/O port SCK31 (Serial clock input/output for CSI31) PMC01 P01 pin operation mode specification I/O port...
Page 115 Chapter 4 Port Functions (e) Pull-up resistor option register 0 (PU0) This is an 8-bit register used to set whether to use an on-chip pull-up resistor. This register can be read and written in 8-bit or 1-bit units. Figure 4-7: Pull-up Resistor Option Register 0 (PU0) Format Symbol Address After reset...
Page 116 Chapter 4 Port Functions (g) External interrupt falling edge specification register 0 (INTF0) This is an 8-bit register used to specify detection of the falling edge for the external interrupt pin. This register can be read and written in 8-bit or 1-bit units. Cautions: 1.
Page 117: Table 4-4: Valid Edge Specification
Chapter 4 Port Functions (h) External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register used to specify detection of the rising edge for the external interrupt pin. This register can be read and written in 8-bit or 1-bit units. Cautions: 1.
Page 118: Port 1
Chapter 4 Port Functions 4.3.4 Port 1 Port 1 is a 3-bit port for which I/O settings can be controlled in 1-bit units. Port 1 functions • 3-bit I/O port • Port input/output specifiable in 1-bit units by port mode register 1 (PM1) •...
Page 119 Chapter 4 Port Functions (b) Port mode register 1 (PM1) This is an 8-bit register used to specify the input mode/output mode. This register can be read and written in 8-bit or 1-bit units. Figure 4-12: Port Mode Register 1 (PM1) Format Symbol Address After reset...
Page 120 Chapter 4 Port Functions (d) Port function control register 1 (PFC1) This is an 8-bit register used to specify control mode 1, 2 and 3 with PFCE1. This register can be read and written in 8-bit or 1-bit units. Figure 4-14: Port Function Control Register 1 (PFC1) Format Symbol Address After reset...
Page 121 Chapter 4 Port Functions (g) Pull-up resistor option register 1 (PU1) This is an 8-bit register used to set whether to use an on-chip pull-up resistor. This register can be read and written in 8-bit or 1-bit units. Figure 4-16: Pull-up Resistor Option Register 1 (PU1) Format Symbol Address After reset...
Page 122 Chapter 4 Port Functions (i) External interrupt falling edge specification register 1 (INTF1) This is an 8-bit register used to specify detection of the falling edge for the external interrupt pin. This register can be read and written in 8-bit or 1-bit units. Cautions: 1.
Page 123: Table 4-5: Valid Edge Specification
Chapter 4 Port Functions (j) External interrupt rising edge specification register 1 (INTR1) This is an 8-bit register used to specify detection of the rising edge for the external interrupt pin. This register can be read and written in 8-bit or 1-bit units. Cautions: 1.
Page 124: Port 3
Chapter 4 Port Functions 4.3.5 Port 3 Port 3 is a 9-bit port for which I/O settings can be controlled in 1-bit units. Port 3 functions • 9-bit I/O port • Port input/output specifiable in 1-bit units by port mode register 3 (PM3) •...
Page 125 Chapter 4 Port Functions Registers (a) Port register 3 (P3) Port register 3 (P3) is a 16-bit register used to control pin level read and output level write. This register can be read and written in16-bit, 8-bit and 1-bit units. However, when using the higher 8 bits of the P3 register as the P3H register and the lower 8 bits as the P3L register, P3 becomes two 8-bit registers for which I/O can be manipulated in 8-bit or 1-bit units.
Page 126 Chapter 4 Port Functions (b) Port mode register 3 (PM3) This is a 16-bit register used to specify the input mode/output mode. This register can be read and written only in 16-bit units. However, when using the higher 8 bits of the PM3 register as the PM3H register and the lower 8 bits as the PM3L register, PM3 can be read and written in 8-bit and 1-bit units.
Page 127 Chapter 4 Port Functions (c) Port mode control register 3 (PMC3) This is a 16-bit register used to specify the port mode/control mode. This register can be read and written only in 16-bit units. However, when using the higher 8 bits of the PMC3 register as the PMC3H register and the lower 8 bits as the PMC3L register, PMC3 can be read and written in 8-bit and 1-bit units.
Page 128 Chapter 4 Port Functions Figure 4-22: Port Mode Control Register 3 (PMC3) Format (2/2) PMC33 P33 pin operation mode specification I/O port CTXD0 (Serial transmit data output for aFCAN0) PMC32 P32 pin operation mode specification I/O port ASCKA0 /[TXDA0]/(CS312) (Serial clock input for UARTA0 / Serial output for UARTA0 / Chip select0 for CSI31) PMC31 P31 pin operation mode specification...
Page 129 Chapter 4 Port Functions (e) Port function control expansion register 3 (PFCE3) This is an 8-bit register used to specify control mode 1, 2 / control mode 3. This register can be read and written in 8-bit or 1-bit units. Figure 4-24: Port Function Control Expansion Register 3 (PFCE3) Format Symbol Address...
Page 130 Chapter 4 Port Functions (g) Pull-up resistor option register 3 (PU3) This is a 16-bit register used to set whether to use an on-chip pull-up resistor. This register can be read and written only in 16-bit units. However, when using the higher 8 bits of the PU3 register as the PU3H register and the lower 8 bits as the PU3L register, PU3 can be read and written in 8-bit and 1-bit units.
Page 131 Chapter 4 Port Functions (i) External interrupt falling edge specification register 3 (INTF3) This is an 8-bit register used to specify detection of the falling edge for the external interrupt pin. This register can be read and written only in 16-bit units. Cautions: 1.
Page 132: Table 4-6: Valid Edge Specification
Chapter 4 Port Functions (j) External interrupt rising edge specification register 3 (INTR3) This is an 8-bit register used to specify detection of the rising edge for the external interrupt pin. This register can be read and written only in 16-bit units. Cautions: 1.
Page 133: Port 4
Chapter 4 Port Functions 4.3.6 Port 4 Port 4 is a 3-bit port for which I/O settings can be controlled in 1-bit units. Port 4 functions • 3-bit I/O port • Port input/output specifiable in 1-bit units by port mode register 4 (PM4) •...
Page 134 Chapter 4 Port Functions (b) Port mode register 4 (PM4) This is an 8-bit register used to specify the input mode/output mode. This register can be read and written in 8-bit or 1-bit units. Figure 4-30: Port Mode Register 4 (PM4) Format Symbol Address After reset...
Page 135 Chapter 4 Port Functions (d) Pull-up resistor option register 4 (PU4) This is an 8-bit register used to set whether to use an on-chip pull-up resistor. This register can be read and written in 8-bit or 1-bit units. Figure 4-32: Pull-up Resistor Option Register 4 (PU4) Format Symbol Address After reset...
Page 136: Port 5
Chapter 4 Port Functions 4.3.7 Port 5 Port 5 is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port 5 functions • 6-bit I/O port • Port input/output specifiable in 1-bit units by port mode register 5 (PM5) •...
Page 137 Chapter 4 Port Functions (b) Port mode register 5 (PM5) This is an 8-bit register used to specify the input mode/output mode. This register can be read and written in 8-bit or 1-bit units. Figure 4-35: Port Mode Register 5 (PM5) Format Symbol Address After reset...
Page 138 Chapter 4 Port Functions Figure 4-36: Port Mode Control Register 5 (PMC5) Format (2/2) PMC52 P52 pin operation mode specification I/O port TIQ03/TOQ03 (TMQ0 input3 / TMQ0 output3) PMC51 P51 pin operation mode specification I/O port TIQ02/TOQ02 (TMQ0 input2 / TMQ0 output2) PMC50 P50 pin operation mode specification I/O port...
Page 139 Chapter 4 Port Functions (e) P5 pin control mode settings PFC53 P53 Pin Control Mode Specification TIQ00 input (TMQ0 input0) TOQ00 output (TMQ0 output0) PFC52 P52 Pin Control Mode Specification TIQ03 input (TMQ0 input3) TOQ03 output (TMQ0 output3) PFC51 P51 Pin Control Mode Specification TIQ02 input (TMQ0 input2) TOQ02 output (TMQ0 output2) PFC50...
Page 140 Chapter 4 Port Functions (g) Pull-down resistor option register 5 (PD5) This is an 8-bit register used to set whether to use an on-chip pull-down resistor. This register can be read and written in 8-bit or 1-bit units. Figure 4-39: Pull-down Resistor Option Register 5 (PD5) Format Symbol Address After reset...
Page 141: Port 7
Chapter 4 Port Functions 4.3.8 Port 7 Port 7 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 7 functions • 16-bit I/O port • Port input/output specifiable in 1-bit units by port mode register 7 (PM7) See Table 4-8, “Port Type,”...
Page 142 Chapter 4 Port Functions (b) Port mode register 7H, port mode register 7L (PM7H, PM7L) These are 8-bit registers used to specify the input mode/output mode. These registers can be read and written in 8-bit or 1-bit units. 16-bit access is not possible. Figure 4-41: Port Mode Register 7H, Port Mode Register 7L (PM7H, PM7L)Format Symbol Address...
Page 143: Port 9
Chapter 4 Port Functions 4.3.9 Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 functions • 16-bit I/O port • Port input/output specifiable in 1-bit units by port mode register 9 (PM9) •...
Page 144 Chapter 4 Port Functions Registers (a) Port register 9 (P9) Port register 9 (P9) is a 16-bit register used to control pin level read and output level write. This register can be read and written in 8-bit and 1-bit units. However, when using the higher 8 bits of the P9 register as the P9H register and the lower 8 bits as the P9L register, P9 becomes two 8-bit registers for which I/O can be manipulated in 8-bit or 1-bit units.
Page 145 Chapter 4 Port Functions (b) Port mode register 9 (PM9) This is a 16-bit register used to specify the input mode/output mode. This register can be read and written only in 16-bit units. However, when using the higher 8 bits of the PM9 register as the PM9H register and the lower 8 bits as the PM9L register, PM9 can be read and written in 8-bit and 1-bit units.
Page 146 Chapter 4 Port Functions Figure 4-44: Port Mode Control Register 9 (PMC9) Format (2/3) PMC915 P915 pin operation mode specification I/O port Note TIP11/TOP11/INTP6/AD15 (TMP1 input1 / TMP1 output1 / Note External interrupt input6 / Address/Data bus I/O PMC914 P914 pin operation mode specification I/O port Note TIP10/TOP10/INTP5/AD14...
Page 147 Chapter 4 Port Functions Figure 4-44: Port Mode Control Register 9 (PMC9) Format (3/3) PMC96 P96 pin operation mode specification I/O port TXDA1/(CS300) (Serial output for UARTA1 / Chip select 0 for CSI30) PMC95 P95 pin operation mode specification I/O port RXDA1/(SCK30) (Serial input for UARTA1 / Serial clock input/output for CSI30) PMC94...
Page 148 Chapter 4 Port Functions (d) Port function control register 9 (PFC9) This is a 16-bit register used to specify control mode 1, 2, 3 and 4 with PFCE9. This register can be read and written only in 16-bit units. However, when using the higher 8 bits of the PFC9 register as the PFC9H register and the lower 8 bits as the PFC9L register, PFC9 can be read and written in 8-bit and 1-bit units.
Page 149 Chapter 4 Port Functions (f) P9 pin control mode settings PFCE915 PFC915 P915 Pin Control Mode Specification INTP6 TOP11 TIP11 Note AD15 PFCE914 PFC914 P914 Pin Control Mode Specification INTP5 TOP10 TIP10 Note AD14 Note: AD14 and AD15 are only for the µPD70F3403 and µPD70F3403A PFCE913 PFC913 P913 Pin Control Mode Specification...
Page 150 Chapter 4 Port Functions PFC95 P95 Pin Control Mode Specification RxDA1/(SCK30) RxDA1 PFC94 P95 Pin Control Mode Specification CS303 ASCKA1 PFCE93 PFC93 P93 Pin Control Mode Specification CS302 TOQ10 TIQ10 Setting prohibited PFCE92 PFC92 P92 Pin Control Mode Specification CS301 TOQ13 TIQ13 Setting prohibited...
Page 151 Chapter 4 Port Functions (g) Pull-up resistor option register 9 (PU9) This is a 16-bit register used to set whether to use an on-chip pull-up resistor. This register can be read and written only in 16-bit units. However, when using the higher 8 bits of the PU9 register as the PU9H register and the lower 8 bits as the PU9L register, PU9 can be read and written in 8-bit and 1-bit units.
Page 152 Chapter 4 Port Functions (h) Pull-down resistor option register 9 (PD9) This is a 16-bit register used to set whether to use an on-chip pull-down resistor. This register can be read and written only in 16-bit units. However, when using the higher 8 bits of the PD9 register as the PD9H register and the lower 8 bits as the PUD9L register, PD9 can be read and written in 8-bit and 1-bit units.
Page 153 Chapter 4 Port Functions (i) External interrupt falling edge specification register 9H (INTF9H) This is an 8-bit register used to specify detection of the falling edge for the external interrupt pin. This register can be read and written in 8-bit or 1-bit units. Cautions: 1.
Page 154: Table 4-7: Valid Edge Specification
Chapter 4 Port Functions (j) External interrupt rising edge specification register 9H (INTR9H) This is an 8-bit register used to specify detection of the rising edge for the external interrupt pin. This register can be read and written in 8-bit or 1-bit units. Cautions: 1.
Page 155: Port Cm
Chapter 4 Port Functions 4.3.10 Port CM Port CM is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CM functions • 4-bit I/O port • Port input/output specifiable in 1-bit units by port mode register CM (PMCM) •...
Page 156 Chapter 4 Port Functions (b) Port mode register CM (PMCM) This is an 8-bit register used to specify the input mode/output mode. This register can be read and written in 8-bit or 1-bit units. Figure 4-52: Port Mode Register CM (PMCM) Format Symbol Address After reset...
Page 157 Chapter 4 Port Functions (c) Port mode control register CM (PMCCM) This is an 8-bit register used to specify the port mode/control mode. It can be read and written in 8-bit or 1-bit units. Remark: External bus functions are only valid for the µPD70F3403 and µPD70F3403A Figure 4-53: Port Mode Control Register CM (PMCCM) Format Symbol Address...
Page 158 Chapter 4 Port Functions (d) Pull-up resistor option register CM (PUCM) This is an 8-bit register used to set whether to use an on-chip pull-up resistor. This register can be read and written in 8-bit or 1-bit units. Figure 4-54: Pull-up Resistor Option Register CM (PUCM) Format Symbol Address After reset...
Page 159: Port Cs
Chapter 4 Port Functions 4.3.11 Port CS Port CS is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port CS functions • 2-bit I/O port • Port input/output specifiable in 1-bit units by port mode register CS (PMCS) •...
Page 160 Chapter 4 Port Functions (b) Port mode register CS (PMCS) This is an 8-bit register used to specify the input mode/output mode. This register can be read and written in 8-bit or 1-bit units. Figure 4-57: Port Mode Register CS (PMCS) Format Symbol Address After reset...
Page 161 Chapter 4 Port Functions (d) Pull-up resistor option register CS (PUCS) This is an 8-bit register used to set whether to use an on-chip pull-up resistor. This register can be read and written in 8-bit or 1-bit units. Figure 4-59: Pull-up Resistor Option Register CS (PUCS) Format Symbol Address After reset...
Page 162: Port Ct
Chapter 4 Port Functions 4.3.12 Port CT Port CT is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT functions • 4-bit I/O port • Port input/output specifiable in 1-bit units by port mode register CT (PMCT) •...
Page 163 Chapter 4 Port Functions (b) Port mode register CT (PMCT) This is an 8-bit register used to specify the input mode/output mode. This register can be read and written in 8-bit or 1-bit units. Figure 4-62: Port Mode Register CT (PMCT) Format Symbol Address After reset...
Page 164 Chapter 4 Port Functions (c) Port mode control register CT (PMCCT) This is an 8-bit register used to specify the port mode/control mode. It can be read and written in 8-bit or 1-bit units. Remark: External bus functions are only valid for the µPD70F3403 and µPD70F3403A Figure 4-63: Port Mode Control Register CT (PMCCT) Format Symbol Address...
Page 165 Chapter 4 Port Functions (d) Pull-up resistor option register CT (PUCT) This is an 8-bit register used to set whether to use an on-chip pull-up resistor. This register can be read and written in 8-bit or 1-bit units. Figure 4-64: Pull-up Resistor Option Register CT (PUCT) Format Symbol Address After reset...
Page 166: Port Dl
Chapter 4 Port Functions 4.3.13 Port DL Port DL is a 14-bit port for which I/O settings can be controlled in 1-bit units. Port DL functions • 14-bit I/O port • Port input/output specifiable in 1-bit units by port mode register DL (PMDL) •...
Page 167 Chapter 4 Port Functions (b) Port mode register DL (PMDL) This is a 16-bit register used to specify the input mode/output mode. This register can be read and written only in 16-bit units. However, when using the higher 8 bits of the PMDL register as the PMDLH register and the lower 8 bits as the PMDLL register, PMDL can be read and written in 8-bit and 1-bit units.
Page 168 Chapter 4 Port Functions (c) Port mode control register (PMCDL) This is a 16-bit register used to specify the port mode/control mode. This register can be read and written only in 16-bit units. However, when using the higher 8 bits of the PMCDL register as the PMCDLH register and the lower 8 bits as the PMCDLL register, PMCDL can be read and written in 8-bit and 1-bit units.
Page 169: Port Function Operation
Chapter 4 Port Functions 4.4 Port Function Operation The port operation differs according to the I/O mode settings, as follows. 4.4.1 Write to I/O ports Output mode Values are written to output latches using transfer instructions. Moreover, the output latch contents are output to the pin.
Page 170: Port Type
Chapter 4 Port Functions 4.5 Port Type Table 4-8: Port Type (1/3) Note 1 Pin name Alternate Function Port block Type SI31 E-SD1 SO31 E-SD4 SCK31 E-SD7E Port 0 CS310 E-SDW4 CS311 E-SD4 CS312/INTP2 N-SDW7 CS313/INTP3 N-SD7 INTP0 L-SD1 Port 1 TIP31/TOP31 G-SD7 TIP30/TOP30/ADTRG...
Page 171 Chapter 4 Port Functions Table 4-8: Port Type (2/3) Note 1 Pin name Alternate Function Port block Type TIQ11/TOQ11/SCK30 U-SDW11E TIQ12/TOQ12/CS300 U-SDW10 TIQ13/TOQ13/CS301 U-SDW10 TIQ10/TOQ10/CS302 U-SDW10 ASCKA1/CS303 G-SD7A RXDA1/(SCK30) G-SDW8E TXDA1/(CS300) G-SDW6 SIB1/{DDI} G-SDJ2 Port 9 SOB1/{DCK} G-SDJ5 SCKB1/{DMS} G-SDJ8E P910 {CS301}/{DDO} E-SWJ7...
Page 172 Chapter 4 Port Functions Table 4-8: Port Type (3/3) Note 1 Pin name Alternate Function Port block Type PDL0 D-7E/B (70F3402) PDL1 D-7E/B (70F3402) PDL2 D-7E/B (70F3402) PDL3 D-7E/B (70F3402) PDL4 D-7E/B (70F3402) Note 4 PDL5 D-7E/B (70F3402) AD5/FLMD1 PDL6 D-7E/B (70F3402) Port DL PDL7...
Page 173: Port Block Types
Chapter 4 Port Functions 4.6 Port Block Types 4.6.1 Port block type E-SD1 Figure 4-69: Type E-SD1 Block Diagram PUmn PMCmn PMmn PORT Address Input signal on control mode PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 174: Port Block Type E-Sd4
Chapter 4 Port Functions 4.6.2 Port block type E-SD4 Figure 4-70: Type E-SD4 Block Diagram PUmn PMCmn PMmn Output signal on control mode PORT Address PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 175: Port Block Type E-Sd7E
Chapter 4 Port Functions 4.6.3 Port block type E-SD7E Figure 4-71: Type E-SD7E Block Diagram Output signal on control mode PUmn PMCmn PMmn Output signal on control mode PORT Address Input signal on control mode PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 176: Port Block Type E-Sdw4
Chapter 4 Port Functions 4.6.4 Port block type E-SDW4 Figure 4-72: Type E-SDW4 Block Diagram PSWAP[0 PSWAP[1 PUmn PMCmn PMmn Output signal on PORT control mode Address PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 177: Port Block Type N-Sdw7
Chapter 4 Port Functions 4.6.5 Port block type N-SDW7 Figure 4-73: Type N-SDW7 Block Diagram PSWAP PUmn INTR INTR mn INTF INTFmn PF C PFCmn PMCmn PMmn Output signal on control mode PORT Address Input signal on Noise eliminate control mode Edge detection PDmn N ch...
Page 178: Port Block Type N-Sd7
Chapter 4 Port Functions 4.6.6 Port block type N-SD7 Figure 4-74: Type N-SD7 Block Diagram PUmn INTR INTR mn INTF INTFmn PF C PFCmn PMCmn PMmn Output signal on control mode PORT Address Input signal on Noise eliminate control mode Edge detection PDmn N ch...
Page 179: Port Block Type L-Sd1
Chapter 4 Port Functions 4.6.7 Port block type L-SD1 Figure 4-75: Type L-SD1 Block Diagram PUmn INTR INTR mn INTF INTFmn PMCmn PMmn PORT Address Input signal on Noise eliminate control mode Edge detection PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 180: Port Block Type G-Sd7
Chapter 4 Port Functions 4.6.8 Port block type G-SD7 Figure 4-76: Type G-SD7 Block Diagram PUmn PF C PFCmn PMCmn PMmn Output signal on control mode PORT Address Input signal on control mode PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 181: Port Block Type U-Sd8
Chapter 4 Port Functions 4.6.9 Port block type U-SD8 Figure 4-77: Type U-SD8 Block Diagram PUmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal on control mode PORT Address Input signal-1 on control mode Input signal-2 on control mode PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com...
Page 182: Port Block Type N-Sd2
Chapter 4 Port Functions 4.6.10 Port block type N-SD2 Figure 4-78: Type N-SD2 Block Diagram PUmn INTR INTR mn INTF INTFmn PF C PFCmn PMCmn PMmn PORT Address PDmn N ch Noise eliminate Input signal-1 on control mode Edge detection Input signal-2 on control mode (Active low)
Page 183: Port Block Type E-Sdw10
Chapter 4 Port Functions 4.6.11 Port block type E-SDW10 Figure 4-79: Type E-SDW10 Block diagram PSWAP[0] PUmn PMCmn PMmn PSWAP[1] Output signal 1 on control mode Output signal 2 on control mode PORT Address Input signal 1 on control mode PDmn N ch User’s Manual U16702EE3V2UD00...
Page 184: Port Block Diagram E-Sd1L
Chapter 4 Port Functions 4.6.12 Port block diagram E-SD1L Figure 4-80: Type E-SD1L Block Diagram PUmn PMCmn PMmn PORT Address Input signal on control mode (Active low) PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 185: Port Block Type W-Sdw11
Chapter 4 Port Functions 4.6.13 Port block type W-SDW11 Figure 4-81: Type W-SDW11 Block Diagram PSWAP[0] PSWAP[1] PUmn INTR INTR mn INTF INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal-1 on control mode PORT Output signal-2 on control mode Address PDmn N ch Noise eliminate...
Page 186: Port Block Type E-Sd7
Chapter 4 Port Functions 4.6.14 Port block type E-SD7 Figure 4-82: Type E-SD7 Block Diagram PUmn PMCmn PMmn Output signal on control mode PORT Address Input signal on control mode PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 187: Port Block Type A-1
Chapter 4 Port Functions 4.6.15 Port block type A-1 Figure 4-83: Type A-1 Block Diagram PMmn PORT Address ANIn User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 188: Port Block Type U-Sdw11E
Chapter 4 Port Functions 4.6.16 Port block type U-SDW11E Figure 4-84: Type U-SDW11E Block Diagram PSWAP[1] PUmn Output enable signal PFCE of control mode PFCEmn PFCmn PMCmn PMmn Output signal-2 on control mode Output signal-1 PORT on control mode Address Input signal-1 on control mode Input signal-2...
Page 189: Port Block Type G-Sd7A
Chapter 4 Port Functions 4.6.17 Port block type G-SD7A Figure 4-85: Type G-SD7A Block Diagram PUmn PF C PFCmn PMCmn PMmn Output signal on control mode PORT Address Input signal on control mode PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 190: Port Block Type G-Sdw8E
Chapter 4 Port Functions 4.6.18 Port block type G-SDW8E Figure 4-86: Type G-SDW8E Block Diagram PUmn Output enable signal PFCmn of control mode PMCmn PMmn Output signal on control mode PORT Address Input signal-1 on control mode (Active low) Input signal-2 on control mode PDmn N ch...
Page 191: Port Block Type G-Sd6
Chapter 4 Port Functions 4.6.19 Port block type G-SD6 Figure 4-87: Type G-SD6 Block Diagram PSWAP[1] PUmn PFCmn PMCmn PMmn Output signal 1A on control mode Output signal 1B on control mode Output signal 2 PORT on control mode Address PDmn N ch User’s Manual U16702EE3V2UD00...
Page 192: Port Block Type G-Sdj2
Chapter 4 Port Functions 4.6.20 Port block type G-SDJ2 Figure 4-88: Type G-SDJ2 Block Diagram Output enable signal 2 on OSD mode PUmn PFCmn PMCmn PMmn PORT Address Input signal-1 on control mode Input signal-2 on control mode (Active low) (Active low) PDmn N ch...
Page 193: Port Block Type G-Sdj5
Chapter 4 Port Functions 4.6.21 Port block type G-SDJ5 Figure 4-89: Type G-SDJ5 Block Diagram Output enable signal on OSD mode PUmn PFCmn PMCmn PMmn Output signal 1 on control mode Output signal 2 on PORT control mode Address (Active low) PDmn N ch User’s Manual U16702EE3V2UD00...
Page 194: Port Block Type G-Sdj8E
Chapter 4 Port Functions 4.6.22 Port block type G-SDJ8E Figure 4-90: Type G-SDJ8E Block Diagram Output enable signal 1 on control mode PUmn PFCmn PMCmn PMmn Output signal-1 on control mode PORT Address Input signal-1 on control mode Input signal-2 on control mode Input enable signal on OCD mode...
Page 195: Port Block Type E-Dwj4
Chapter 4 Port Functions 4.6.23 Port block type E-DWJ4 Figure 4-91: Type E-DWJ4 Block Diagram PSWAP[0] OCDM0 OCDM0 PMCmn PMmn Output signal on control mode PORT Address DRST TRSTZIN PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 196: Port Block Type U-Sdw11
Chapter 4 Port Functions 4.6.24 Port block type U-SDW11 Figure 4-92: Type U-SDW11 Block Diagram PSWAP[1] PUmn PFCE Output enable signal of control mode PFCEmn PFCmn PMCmn PMmn Output signal-1 on control mode Output signal-2 PORT on control mode Address Input signal-1 on control mode Input signal-2...
Page 197: Port Block Type W-Sd11
Chapter 4 Port Functions 4.6.25 Port block type W-SD11 Figure 4-93: Type W-SD11 Block Diagram PUmn INTR INTR mn INTF INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal-1 on control mode Output signal-2 on control mode PORT Address PDmn N ch Noise eliminate Input signal-2 on control mode...
Page 198: Port Block Type W-Sd12E
Chapter 4 Port Functions 4.6.26 Port block type W-SD12E Figure 4-94: Type W-SD12E Block Diagram PUmn INTR INTR mn Output enable signal INTF on control mode INTFmn PFCE PFCEmn PFCmn 0: Port 1: control mode PMCmn PMmn Output signal-1 on control mode Output signal-2 on control mode PORT...
Page 199: Port Block Type U-Sdw10
Chapter 4 Port Functions 4.6.27 Port block type U-SDW10 Figure 4-95: Type U-SDW10 Block Diagram PSWAP[1] PUmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal-1 on control mode Output signal-2 PORT on control mode Address Input signal on control mode PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from...
Page 200: Port Block Type G-Sdw6
Chapter 4 Port Functions 4.6.28 Port Block type G-SDW6 Figure 4-96: Type G-SDW6 Block Diagram PSWAP[1] PUmn PFCmn PMCmn PMmn Output signal 1A on control mode Output signal 1B on control mode Output signal 2 PORT on control mode Address PDmn N ch User’s Manual U16702EE3V2UD00...
Page 201: Port Block Type E-D1
Chapter 4 Port Functions 4.6.29 Port block type E-D1 Figure 4-97: Type E-D1 Block Diagram PUmn PMCmn PMmn PORT Address Input signal on control mode PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 202: Port Block Type E-D4
Chapter 4 Port Functions 4.6.30 Port block type E-D4 Figure 4-98: Type E-D4 Block Diagram PUmn PMCmn PMmn Output signal on control mode PORT Address PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 203: Port Block Type D-7E
Chapter 4 Port Functions 4.6.31 Port block type D-7E Figure 4-99: Type D-7E Block Diagram Output enable signal on control mode PMCmn PMmn Output signal on control mode PORT Address Input signal on control mode User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 204: Port Block Type C-D1
Chapter 4 Port Functions 4.6.32 Port block type C-D1 Figure 4-100: Type C-D1 Block Diagram PUmn PMmn PORT Address PDmn N ch User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 205: Port Block Type B
Chapter 4 Port Functions 4.6.33 Port block type B Figure 4-101: Type B Block Diagram PMmn PORT Address User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 206 [MEMO] User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 207: Chapter 5 Bus Control Function
Chapter 5 Bus Control Function The µPD70F3403 and µPD70F3403A are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. Cautions: 1. Do not set up any external bus interface configuration to the µPD70F3402. 2.
Page 208: Bus Control Pins
AD0 to AD15 undefined Hi-Z Inactive 5.2.2 Pin status in each operation mode For the pin status of the V850E/RS1 in each operation mode, refer to 2.3 ”Description of Pin Func- tions” on page 45. User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com...
Page 209: Memory Block Function
Chapter 5 Bus Control Function 5.3 Memory Block Function The 64 MB memory space is divided into memory blocks of 2 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. Figure 5-1: Data Memory Map 3FF FFFFH 3FF FFFFH...
Page 210: Chip Select Control Function
Table 5-3. By using these chip select control functions, the memory block can be divided to enable effective use of the memory space. However, since the V850E/RS1 has sixteen address pins (PDL0/AD0 to PDL15/AD15), 64 KB addresses can be selected linearly.
Page 211: Bus Access
Chapter 5 Bus Control Function 5.4 Bus Access 5.4.1 Number of clocks for access The following table shows the number of base clocks required for accessing each resource. Area (Bus Width) Internal ROM (32 bits) Internal RAM (32 bits) External Memory (16 bits) Area (Bus Width) Bus Cycle Type Note 1...
Page 212: Bus Size Setting Function
The bus size of each external memory area selected by CSn can be set (to 8 bits or 16 bits) by using the BSC register. The external memory area of the V850E/RS1 (0000000H to 03FFFFFH) is selected by CS0 and CS1. Bus size configuration register (BSC) This register can be read or written in 16-bit units.
Page 213: Access By Bus Size
Chapter 5 Bus Control Function 5.4.3 Access by bus size The V850E/RS1 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits.
Page 214 Chapter 5 Bus Control Function Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1-st Access 2-nd Access Address Address Address 2n + 1 2n + 1 2n + 2 Halfword External...
Page 215 Chapter 5 Bus Control Function Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) 1-st Access 2-nd Access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data External data bus data bus...
Page 216 Chapter 5 Bus Control Function (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) 1-st Access 2-nd Access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data External data bus data bus...
Page 217 Chapter 5 Bus Control Function (b) 8-bit data bus width (1/2) <1> Access to address (4n) 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data External Word data...
Page 218 Chapter 5 Bus Control Function (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data...
Page 219: Wait Function
Chapter 5 Bus Control Function 5.5 Wait Function 5.5.1 Programmable wait function Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each CS space. The number of wait states can be programmed for each chip select area (CS0, CS1) by using data wait control register 0 (DWC0).
Page 220: External Wait Function
Chapter 5 Bus Control Function 5.5.2 External wait function To synchronize an extremely slow external device, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function.
Page 221: Programmable Address Wait Function
Chapter 5 Bus Control Function 5.5.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control register (AWC). Address wait insertion is set for each chip select area (CS0, CS1). If an address setup wait is inserted, it seems that the high-clock period of T1 state is extended by 1 clock.
Page 222: Idle State Insertion Function
Chapter 5 Bus Control Function 5.6 Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select function in the multiplexed address/data bus mode.
Page 223: Bus Hold Function
Chapter 5 Bus Control Function 5.7 Bus Hold Function 5.7.1 Functional outline The HLDAK and HLDRQ functions are valid if the PCM2 and PCM3 pins are set in the control mode. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
Page 224: Bus Hold Procedure
Chapter 5 Bus Control Function 5.7.2 Bus hold procedure The bus hold status transition procedure is shown below. Figure 5-8: Bus Hold Status Transition Procedure ¯¯¯¯¯¯¯ <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3>...
Page 225: Bus Priority
ROM area to the external memory area. 5.9.2 Data space The V850E/RS1 has an address misalign function. With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop.
Page 226: Bus Timing
Chapter 5 Bus Control Function 5.10 Bus Timing Read cycle Figure 5-9: Bus Read Timing (Bus Size: 16 bit, 16-bit Access) CLKOUT AD15-AD0 ASTB WAIT Programmable External IDLE wait wait state In the case of Odd address Even address 8-bit access AD15 to AD8 Data AD7 to AD0...
Page 227 Chapter 5 Bus Control Function Figure 5-10: Bus Read Timing (Bus Size: 8 bit) CLKOUT AD15-AD8 AD7-AD0 ASTB WAIT Programmable External IDLE wait wait state Remarks: 1. The circles indicate the sampling timing when 0 is set for the programmable wait. 2.
Page 228 Chapter 5 Bus Control Function Write cycle Figure 5-11: Bus Write Timing (Bus Size: 16 bit, 16-bit Access) CLKOUT AD15-AD0 ASTB WAIT WR1-WR0 Programmable External IDLE wait wait state In the case of Odd address Even address 8-bit access AD15 to AD8 Data Undefined AD7 to AD0...
Page 229 Chapter 5 Bus Control Function Figure 5-12: Bus Write Timing (Bus Size: 8 bit) CLKOUT AD15-AD8 AD7-AD0 ASTB WAIT WR1-WR0 Programmable External IDLE wait wait state Note: WR0 and WR1 output a low level as shown in the above timing chart when target data access is performed.
Page 230 Chapter 5 Bus Control Function Figure 5-13: Address Wait Timing (Bus Size: 16 bit) TASW TAHW CLKOUT Address Data AD15-AD0 ASTB WAIT WR1-WR0 Note: WR0 and WR1 output a low level as shown in the above timing chart when target data access is performed.
Page 231 Chapter 5 Bus Control Function Bus hold cycle Figure 5-14: Bus Hold Timing (Bus Size: 16 bit) Note 1 Note 1 CLKOUT HLDRG HLDAK Unde- Unde- AD15-AD0 fined fined ASTB all1 all1 Bus hold Notes: 1. Upon detection of a low level in the T2 and T3 states of HLDRQ (sampling timing), the operation moves on to the bus hold cycle after the T3 state ends.
Page 232 [MEMO] User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 233: Clock Generator
Chapter 6 Clock Generator 6.1 Overview The following clock generation functions are available. • Main clock oscillator • In clock-through mode = 4 to 8 MHz (internal f = 4 to 8 MHz) • In PLL mode = 4 to 8 MHz (internal f = 4 to 40 MHz (µPD70F3403 and µPD70F3403A) = 4 to 32 MHz (µPD70F3402)) •...
Page 234: Configuration
Chapter 6 Clock Generator 6.2 Configuration Figure 6-1: Clock Generator MPCCTL.SELPLL Peripherals PRS1 PSMR (IDLE1) WDT2 BRGC CCLS.CCLSF PSMR (STOP) _MCKSEL_CKDIV Standby PRS2 PCC.MFR control PSMR (HALT) PLL0 (×12) _MCKSEL Output Main OSC control PLL1 (×10) Standby CPUCLK control SystemCLK MPCCTL.STPPLL0 MPCCTL.STPPLL1 OCSK0...
Page 235: Control Registers
Chapter 6 Clock Generator 6.3 Control Registers Main peripheral clock control register (MPCCTL) This is an 8-bit register that selects the internal clock. This register can be read or written in 8-bit or 1-bit units. Data can be written to this register only in combination of specific sequences (refer to 3.2.3 ”Special registers”...
Page 236 Chapter 6 Clock Generator Figure 6-2: Main Peripheral Clock Control Register (MPCCTL) Format (2/2) STPPLL0 PLL 0 execution stop register PLL0 executable (Default) PLL0 stop Cautions: 1. If this bit is set to “1”, it is impossible to set to “0” by register writing. Only RESET input can be set to “0”.
Page 237 Chapter 6 Clock Generator Extension clock select register (EXCKSEL) This is an 8-bit register that selects the internal clock. This register can be read or written in 8-bit or 1-bit units. Figure 6-3: Extension Clock Select Register (EXCKSEL) Format Symbol Address After reset EXCKSEL...
Page 238 Chapter 6 Clock Generator Power save mode register (PSMR) This is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Be sure to clear bits 2 to 7 of the PSMR register to 0.
Page 239 Chapter 6 Clock Generator Processor clock control register (PCC) The processor clock control register (PCC) is a special register. This register can be read or written in 8-bit or 1-bit units. Data can be written to this register only in combination of specific sequences (refer to 3.2.3 ”Special registers”...
Page 240 Chapter 6 Clock Generator CPU operation clock status register (CCLS) Status flags that indicate the operation status of the CPU operating clock. This register can be read in 8-bit or 1-bit units. Figure 6-6: CPU Operation Clock Status Register (CCLS) Format Symbol Address After reset...
Page 241 Chapter 6 Clock Generator Oscillation stabilization time select register (OSTS) This 8-bit register selects the oscillation stabilization time following reset or release of the STOP mode. The OSTS register is set by an 8-bit memory manipulation instruction. RESET input sets this register to 03H. Figure 6-8: Oscillation Stabilization Time Select Register (OSTS) Format Symbol Address...
Page 242 Chapter 6 Clock Generator Clock selection register 2 (OCKS2) This is an 8-bit register that controls the operation enable and clock selection for CSIBn (n = 0, 1). Figure 6-9: Clock Selection Register 2 (OCKS2) Format Symbol Address After reset OCKS2 OCKSEN2 OCKSTH2 OCKS21 OCKS20 FFFFF868H...
Page 243: Pll Function
Chapter 6 Clock Generator 6.4 PLL Function The PLL function is used to output the operating clock of the CPU and peripheral macro at a frequency 10 times (PLL1) / 12 times (PLL0) higher than the oscillation frequency, and selects the clock-through mode.
Page 244 Chapter 6 Clock Generator PLL1 can generate below frequencies from f signal and register setting. PLL1 Output OCKS1 register PLL1 Time CKC Register Base clock (f Note divide value value divide value PLL1 × 10 PLL1 × 5 PLL1 × 2.5 PLL1 ×...
Page 245: Control Register
Chapter 6 Clock Generator 6.4.1 Control register PLL0 control register 0 (PLLCTL0) This is an 8-bit register that enables PLL0 operation. This register can be written in 8-bit units. After reset, an firmware initializes this register to 00H so that the PLL0 is enabled and in a locked status.
Page 246 Chapter 6 Clock Generator PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLL is initialized by writing the value 00H to the PLLCTLn register, and when the software STOP mode is released. This register can be read or written in 8-bit units.
Page 247 Chapter 6 Clock Generator Clock control register (CKC) This is an 8-bit register that controls system clock (f ) when it operates on PLL mode (SELPLL bit of MPCCTL register is set to 1). This register can be read or written in 8-bit or 1-bit units. Be sure to clear bits 2 to 7 of the CKC register to 0.
Page 248 Chapter 6 Clock Generator Clock selection register 0 (OCKS0) This is an 8-bit register that controls the operation enable and clock input selection for PLL0. Figure 6-14: Clock Selection Register 0 (OCKS0) Format Symbol Address After reset OCKS0 OCKSEN0 OCKSTH0 OCKS01 OCKS00 FFFFF860H OCKSEN0 Specified for execution enable...
Page 249 Chapter 6 Clock Generator Clock selection register 1 (OCKS1) This is an 8-bit register that controls the operation enable and clock input selection for PLL1. Figure 6-15: Clock Selection Register 1 (OCKS1) Format Symbol Address After reset OCKS1 OCKSEN1 OCKSTH1 OCKS11 OCKS10 FFFFF864H OCKSEN1 Specified for execution enable...
Page 250: Programmable Clock Output Function (Pcl)
Chapter 6 Clock Generator 6.5 Programmable Clock output Function (PCL) It is possible to output a clock independent from CPU clock on pin P913/TIP20/TOP20/INTP4/PCL. The programmable clock output frequency is equal to f divided by two prescalers (PCLM and PLL_MCKSEL OCKS3 registers).
Page 251 Chapter 6 Clock Generator Clock selection register 3 (OCKS3) This is an 8-bit register that controls the operation enable and clock selection for PCL output. Figure 6-17: Clock Selection Register 3 (OCKS3) Format Symbol Address After reset OCKS3 OCKSEN3 OCKSTH3 OCKS31 OCKS30 FFFFF86CH OCKSEN3 Specified for execution enable...
Page 252: Usage
Chapter 6 Clock Generator 6.6 Usage 6.6.1 To use PLL1 = 4 × f After RESET has been released, the default mode is PLL0 mode (F ). When PLL_MCKSEL operating mode change to PLL1 mode, register access must keep below mentioned order. •...
Page 253: To Use Clock Through Mode
Chapter 6 Clock Generator 6.6.2 To use clock through mode When operating mode change to clock through mode, register access must keep the following order: 1) MPCCTL = 00H‚(MPCCTL: SELPLL bit = 0 2) MPCCTL = 03H‚MPCCTL: STPPLL0 bit = STPPLL1 bit = 0 6.6.3 to Use the programmable clock output function (PCL) When use the PCL function, register setting have 1 sequence.
Page 254: Table 6-3: Divide Value Of F Pll Frequency And F Pcl Frequency
Chapter 6 Clock Generator The follow table shows the divide value of f frequency and f frequency. Table 6-3: Divide Value of f Frequency and f Frequency PCLM register (h) OCKS3 register (h) PCL output signal period 1 (18h) PLL_MCKSEL 2 (10h) PLL_MCKSEL 1(10h)
Page 255: 16-Bit Timer/Event Counter P
Chapter 7 16-Bit Timer/Event Counter P The V850E/RS1 includes four channels Timer P (TMP0, TMP1, TMP2 and TMP3). 7.1 Features Timer P (TMP) is a 16-bit timer/event counter provided with general-purpose functions. TMP can perform the following operations. • 16-bit-accuracy PWM output timer •...
Page 256: Configuration
Chapter 7 16-Bit Timer/Event Counter P 7.3 Configuration TMP includes the following hardware. Table 7-1: Configuration of TMP0 to TMP3 Item Configuration Timer register 16-bit counter TMPn timer capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) Registers TMPn timer read buffer register (TPnCNT) CCR0 buffer register, CCR1 buffer register Timer output TOPn1, TOPn0...
Page 257 Chapter 7 16-Bit Timer/Event Counter P Figure 7-1: Block Diagram of Timer P Internal bus TPnCTL0 TPnIOC2 TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnESS1 TPnESS0 TPnETS1 TPnETS0 TPnCE TPnCCR0 CCR0 buffer TPnCNT0 Load INTTPnCC0 register Note 1 /128 Note 2 RING Clear TPnCE Edge Counter control...
Page 258 Chapter 7 16-Bit Timer/Event Counter P TMP capture/compare register 0 (TPnCCR0) The TPnCCR0 register is a 16-bit register that operates either as capture register or as a compare register. Whether this register is used as a capture register or as a compare register can be specified with the TPnCCS1 and TPnCCSS0 bits of the TMPn option register 0 (TPnOPT0 register), but only in the free-running mode.
Page 259 Chapter 7 16-Bit Timer/Event Counter P TMP capture/compare register 1 (TPnCCR1) The TPnCCR1 register is a 16-bit register that operates either both as a capture register or as a compare register. Whether this register is used as a capture register or as a compare register can be specified with the TPnCCS1 and TPnCCS0 bits of the TMPn option register 0 (TPnOPT0 register), but only in free-running mode.
Page 260 Chapter 7 16-Bit Timer/Event Counter P TMPn counter read buffer register (TPnCNT) TPnCNT register is a read buffer register that can read 16-bit counter values. This register is read-only, using a 16-bit memory manipulation instruction. RESET input sets this register to FFFFH. Although the hardware status is FFFFH when TPnCE bit of TPnCTL0 equals 0, 0000H is read from this register.
Page 261: Control Registers
Chapter 7 16-Bit Timer/Event Counter P 7.4 Control Registers TMPn control register 0 (TPnCTL0) TMPn control register 0 is an 8-bit register that controls the operation of timer P. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 262 Chapter 7 16-Bit Timer/Event Counter P TMPn timer control register 1 (TPnCTL1) TMPn control register 1 is an 8-bit register that controls the operation of timer P. This register can be read and written in 8-bit or 1-bit units. 16-bit access is not possible. RESET input clears this register to 00H.
Page 263 Chapter 7 16-Bit Timer/Event Counter P Figure 7-6: TMPn Control Register 1 (TPnCTL1) Format (2/2) TPnEEE Count clock selection Use the internal clock (clock selected with TPnCKS2 to TPnCKS0 bits of TPnCTL0 register) Use external clock (TIPn0 input edge) The valid edge is specified with TPnEES1 and TPnEES0 bits when TPnEEE bit = 1 (external clock TIPn0).
Page 264 Chapter 7 16-Bit Timer/Event Counter P TMPn dedicated I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Figure 7-7: TMPn Dedicated I/O Control Register 0 (TPnIOC0) Format Address: TP0IOC0: FFFFF592H, TP1IOC0: FFFFF5A2H TP2IOC0: FFFFF5B2H, TP3IOC0: FFFFF5C2H...
Page 265 Chapter 7 16-Bit Timer/Event Counter P TMPn dedicated I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge for the external input signals (TIPn0 and TIPn1). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 266 Chapter 7 16-Bit Timer/Event Counter P TMP I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge for external event count input signals (TIPn0) and external trigger input signal (TIPn0). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 267 Chapter 7 16-Bit Timer/Event Counter P TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect overflow. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Figure 7-10: TMPn Option Register 0 (TPnOPT0) Format Address: TP0OPT0: FFFFF595H, TP1OPT0: FFFFF5A5H TP2OPT0: FFFFF5B5H, TP3OPT0: FFFFF5C5H...
Page 268 Chapter 7 16-Bit Timer/Event Counter P Selector operation control register 0 (SELCNT0) The SELCNT0 register is an 8-bit register that selects the capture trigger for TMPn. This register can be read or written in 8-bit or 1-bit units. RESET input clears this register to 00H. Figure 7-11: Selector Operation Control Register 0 (SELCNT0) Format After Symbol...
Page 269 Chapter 7 16-Bit Timer/Event Counter P TIPnm pin noise elimination control register n (PnmNFC) The PnmNFC register is an 8-bit register that sets the digital noise filter of the timer P input pin. This register can be read or written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 270: Operation
Chapter 7 16-Bit Timer/Event Counter P 7.5 Operation Timer P can perform the following operations. TPnEST TIPn0 TPnEEE Capture/Compare Compare Operation Software External Count clock Selection Write trigger bit trigger input selection Interval timer mode Invalid Invalid Internal/external Compare only Any time write External event counter Invalid...
Page 271 Chapter 7 16-Bit Timer/Event Counter P Figure 7-13: Flowchart of Basic Operation for Anytime Write START Initial settings Timer operation enable (TPnCE = 1) Transfer of TPnCCR0, TPnCCR1 values to CCR0 buffer register and CCR1 buffer register Rewrite TPnCCR0 Transfer to CCR0 buffer register Rewrite TPnCCR1 Transfer to CCR1 buffer register INTTPnCC0 output...
Page 272 Chapter 7 16-Bit Timer/Event Counter P Figure 7-14: Timing Diagram for Anytime Write TPnCE = 1 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register INTTPnCC0 INTTPnCC1 Remarks: 1. D01, D02: Setting values of TPnCCR0 register (0000H to FFFFH) D11, D12: Setting values of TPnCCR1 register (0000H to FFFFH) 2.
Page 273 Chapter 7 16-Bit Timer/Event Counter P Reload When data is written to the TPnCCR0 and TPnCCR1 registers during timer operation, it is compared with the value of the 16-bit counter via the CCRm buffer register. The values of the TPnCCR0 and TPnCCR1 registers can be rewritten when TPnCE = 1. So that the set values of the TPnCCR0 and TPnCCR1 registers are compared with the value of the 16-bit counter (the set values are reloaded to the CCRm buffer register), the value of the TPnCCR0 register must be rewritten and then a value must be written to the TPnCCR1 register...
Page 274 Chapter 7 16-Bit Timer/Event Counter P Figure 7-16: Timing Chart for Reload TPnCE = 1 16-bit counter TPnCCR0 CCR0 buff er 0000H register Note Same value wr ite TPnCCR1 CCR1 buff er 0000H register Note INTTPnCC0 INTTPnCC1 Note: Reload is not performed because TPnCCR1 register is not written. Remarks: 1.
Page 275: Interval Timer Mode (Tpnmd2 To Tpnmd0 = 000)
Chapter 7 16-Bit Timer/Event Counter P 7.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated upon a match between the setting value of the TPnCCR0 register and the value of the 16-bit counter, and the 16-bit counter is cleared.
Page 276 Chapter 7 16-Bit Timer/Event Counter P Figure 7-18: Basic Operation Timing in Interval Timer Mode (1/2) (a) When D1 > D2 > D3; only TPnCCR0 register value is written, and TOPn0 and TOPn1 are not output (TPnOE0 = 0, TPnOE1 = 0, TPnOL0 = 0, TPnOL1 = 1) TPnCE = 1 FFFFH 16-bit...
Page 277 Chapter 7 16-Bit Timer/Event Counter P Figure 7-18: Basic Operation Timing in Interval Timer Mode (2/2) (b) When D1 = D2; TPnCCR0 and TPnCCR1 are not rewritten, and TOPn0 and TOPn1 are output (TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 1) TPnCE = 1 FFFFH 16-bit...
Page 278: External Event Counter Mode (Tpnmd2 To Tpnmd0 = 001)
Chapter 7 16-Bit Timer/Event Counter P 7.5.3 External event counter mode (TPnMD2 to TPnMD0 = 001) In the external event count mode, the external event count input (TIPn0 pin input) is used as a count-up signal. Regardless of the setting of the TPnEEE bit of the TPnCTL0 register, 16-bit timer/event counter P counts up the external event count input (TIPn0 pin input) when it is set in the external event count mode.
Page 279 Chapter 7 16-Bit Timer/Event Counter P Figure 7-20: Basic Operation Timing in External Event Counter Mode (1/2) (a) When D1 > D2 > D3; rewrite TPnCCR0 only; TOPn1 and TOPn0 are not output (TPnOE0 = 0, TPnOE1 = 0, TPnOL0 = 0, TPnOL1 = 1) TPnCE = 1 FFFFH 16-bit...
Page 280 Chapter 7 16-Bit Timer/Event Counter P Figure 7-20: Basic Operation Timing in External Event Counter Mode (2/2) (b) When D1 = D2; TPnCCR0 and TPnCCR1 are not rewritten, and TOPn0 and TOPn1 are output (TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 1) TPnCE = 1 FFFFH 16-bit...
Page 281: External Trigger Pulse Mode (Tpnmd2 To Tpnmd0 = 010)
Chapter 7 16-Bit Timer/Event Counter P 7.5.4 External trigger pulse mode (TPnMD2 to TPnMD0 = 010) When TPnCE = 1 in the external trigger pulse mode, the 16-bit counter stops at FFFFH and waits for input of an external trigger (TIPn0 pin input). When the counter detects the edge of the external trigger (TIPn0 pin input), it starts counting up.
Page 282 Chapter 7 16-Bit Timer/Event Counter P Figure 7-21: Flowchart of Basic Operation in External Trigger Pulse Output Mode START Initial settings • Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) • External trigger pulse output mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 010) •...
Page 283 Chapter 7 16-Bit Timer/Event Counter P Figure 7-22: Basic Operation Timing in External Trigger Pulse Output Mode (TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) TPnCE = 1 FFFFH 16-bit Note counter External trigger (TIPn0 pin) TPnCCR0 CCR0 buffer 0000H...
Page 284: One-Shot Pulse Mode (Tpnmd2 To Tpnmd0 = 011)
Chapter 7 16-Bit Timer/Event Counter P 7.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011) When TPnCE is set to 1 in the one-shot pulse mode, the 16-bit counter waits for the setting of the TPnEST bit (to 1) or a trigger that is input when the edge of the TIPn0 pin is detected, while holding FFFFH.
Page 285 Chapter 7 16-Bit Timer/Event Counter P Figure 7-23: Flowchart of Basic Operation in One-Shot Pulse Mode START Initial setting • Select clock. (TPnCTL1: TPnEEE = 0) (TPnCTL0: TPnCKS2 to TPnCKS0) • Set one-shot pulse mode. (TPnCTL1: TPnMD2 to TPnMD0 = 011) •...
Page 286 Chapter 7 16-Bit Timer/Event Counter P Figure 7-24: Timing of Basic Operation in One-Shot Pulse Mode (TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) TPnCE = 1 TPnEST = 1 FFFFH Note 16-bit counter External trigger (TIPn0 pin) TPnCCR0 CCR0 buffer...
Page 287: Pwm Mode (Tpnmd2 To Tpnmd0 = 110)
Chapter 7 16-Bit Timer/Event Counter P 7.5.6 PWM mode (TPnMD2 to TPnMD0 = 110) In the PWM mode, TMPn capture/compare register 1 (TPnCCR1) is used to set the duty factor and TMPn capture/compare register 0 (TPnCCR0) is used to set the cycle. By using these two registers and operating the timer, variable-duty PWM is output.
Page 288 Chapter 7 16-Bit Timer/Event Counter P Figure 7-25: Flowchart of Basic Operation in PWM Mode (2/2) (b) When values of TPnCCR0, TPnCCR1 registers are rewritten during timer operation START Initial setting • Select clock. (TPnCTL0: TPnCKS2 to TPnCKS0) • Set PWM mode. (TPnCTL1: TPnMD2 to TPnMD0 = 100) •...
Page 289 Chapter 7 16-Bit Timer/Event Counter P Figure 7-26: Basic Operation Timing in PWM Mode (1/2) (a) When rewriting TPnCCR1 value (TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) TPnCE = 1 FFFFH 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1...
Page 290 Chapter 7 16-Bit Timer/Event Counter P Figure 7-26: Basic Operation Timing in PWM Mode (2/2) (b) When TPnCCR0, TPnCCR1 values are rewritten (TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) TPnCE = 1 FFFFH 16-bit counter TPnCCR0 Note CCR0 buffer...
Page 291: Free-Running Mode (Tpnmd2 To Tpnmd0 = 101)
Chapter 7 16-Bit Timer/Event Counter P 7.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101) In the free-running mode, both the interval function and the compare function can be realized by operating the 16-bit counter as a free-running counter and selecting capture/compare operation with the TPnCCS1 and TPnCCS0 bits.
Page 292 Chapter 7 16-Bit Timer/Event Counter P Figure 7-27: Flowchart of Basic Operation in Free-Running Mode START Initial settings • Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) • Free-running mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 101) TPnCCS1, TPnCCS0 setting TPnCCS1 = 0 TPnCCS1 = 0 TPnCCS1 = 1 TPnCCS1 = 1...
Page 293 Chapter 7 16-Bit Timer/Event Counter P When TPnCCS1 = 0, and TPnCCS0 = 0 settings (interval function description, compare function) When TPnCE = 1 is set, the 16-bit counter counts from 0000H to FFFFH and the free-running count-up operation continues until TPnCE = 0 is set. In this mode, when a value is written to the TPnCCR0 and TPnCCR1 registers, they are transferred to the CCR0 buffer register and the CCR1 buffer register (any time write mode).
Page 294 Chapter 7 16-Bit Timer/Event Counter P When TPnCCS1 = 1 and TPnCCS0 = 1 settings (capture function description) When TPnCE = 1, the 16-bit counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. During this time, values are captured by capture trigger operation and are written to the TPnCCR0 and TPnCCR1 registers.
Page 295 Chapter 7 16-Bit Timer/Event Counter P When TPnCCS1 = 1 and TPnCCS0 = 0 When TPnCE = 1 is set, the counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. The TPnCCR0 register is used as a compare register. An interrupt signal is output upon a match between the value of the 16-bit counter and the setting value transferred to the CCR0 buffer register from the TPnCCR0 register as an interval function.
Page 296 Chapter 7 16-Bit Timer/Event Counter P When TPnCCS1 = 0 and TPnCS0 = 1 When TPnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. The TPnCCR1 register is used as a compare register.
Page 297: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 = 110)
Chapter 7 16-Bit Timer/Event Counter P 7.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) In the pulse width measurement mode, free-running count is performed, and upon detection of both the rising and falling edges of TIPn0, the 16-bit counter value is saved to capture register 0 (TPnCCR0) and the 16-bit counter is cleared to 0000H.
Page 298 Chapter 7 16-Bit Timer/Event Counter P Figure 7-33: Basic Operation Timing in Pulse Width Measurement Mode (TPnOE0 = 0, TPnOE1 = 0, TPnOL0 = 0, TPnOL1 = 0) TPnCE = 1 FFFFH FFFFH 16-bit counter TIPn0 0000H TPnCCR0 INTTPnCC0 Cleared by writing 0 TPnOVF from CPU...
Page 299: Timer Synchronization Operation Function
Timer P and timer Q have a timer synchronized operation function (tuned operation mode). The timers that can be synchronized are listed in Table 7-3 (√ : Settable, ×: Not settable). Table 7-3: Tuned Operation Mode of Timer Master Timer Slave Timer V850E/RS1 √ TMP0 TMP1 √...
Page 300: Table 7-5: Timer Output Functions
Chapter 7 16-Bit Timer/Event Counter P Table 7-5: Timer Output Functions Free-Running Mode PWM Mode Triangular Wave PWM Mode Tuned Timer Tuning Tuning Channel Tuning ON Tuning ON Tuning OFF Tuning ON ← ← ← TOP00 Toggle TMP0 ← ← ←...
Page 301 Chapter 7 16-Bit Timer/Event Counter P Figure 7-34: Tuned Operation Image (TMP2, TMP3, TMQ0) Unit operation Tuned operation TMP2 TMP2 (master) + TMP3 (slave) + TMQ0 (slave) 16-bit timer/counter 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare TOP21 (PWM output) 16-bit capture/compare TOP21 (PWM output) 16-bit capture/compare...
Page 302 Chapter 7 16-Bit Timer/Event Counter P Figure 7-35: Basic Operation Timing of Tuned PWM Function (TMP2, TMP3, TMQ0) FFFFH TMP2 16-bit counter 0000H TP2CE TP3CE TQ0CE TP2CCR0 TP2CCR1 TP3CCR0 TP3CCR1 TQ0CCR0 TQ0CCR1 TQ0CCR2 TQ0CCR3 INTTP2CC0 match interrupt INTTP2CC1 match interrupt INTTP3CC0 match interrupt INTTP3CC1...
Page 303: 16-Bit Timer/Event Counter Q
Chapter 8 16-Bit Timer/Event Counter Q The V850E/RS1 includes two channels 16 bit timer/event counter Q (TMQ0, TMQ1) 8.1 Features Timer Q (TMQ) is a 16-bit timer/event counter provided with general-purpose functions. TMQ can perform the following operations. • 16-bit-accuracy PWM output •...
Page 304: Configuration
Chapter 8 16-Bit Timer/Event Counter Q 8.3 Configuration TMQ includes the following hardware. Table 8-1: TMQ Configuration Item Configuration 16-bit counter × 1 Timer register TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3) Registers TMQn counter read buffer register (TQnCNT) CCR0 to CCR3 buffers registers Note Timer input...
Page 305 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-1: Block Diagram of Timer Q Internal bus TQnCTL0 TQnIOC2 TQnCE TQnCKS2 TQnCKS1 TQnCKS0 TQnESS1 TQnESS0 TQnETS1 TQnETS0 TQnCE TQnCCR0 CCR0 buffer TQnCNT0 Load INTTQnCC0 register /128 Clear TQnCE Edge 16-bit counter Counter control detection INTTQnOV circuit...
Page 306 Chapter 8 16-Bit Timer/Event Counter Q Capture/compare register 0 (TQnCCR0) The TQnCCR0 register is a 16-bit register that has a capture function and a compare function. Whether this register is used as a capture register or a compare register can be specified by using the TQnCCS0 bit of the TQnOPT0 register, but only in the free-running mode.
Page 307 Chapter 8 16-Bit Timer/Event Counter Q Capture/compare register 1 (TQnCCR1) The TQnCCR1 register is a 16-bit register that has a capture function and a compare function. Whether this register is used as a capture register or a compare register can be specified by using the TQnCCS1 bit of the TQnOPT0 register, but only in the free-running mode.
Page 308 Chapter 8 16-Bit Timer/Event Counter Q Capture/compare register 2 (TQnCCR2) The TQnCCR2 register is a 16-bit register that has a capture function and a compare function. Whether this register is used as a capture register or a compare register can be specified by using the TQnCCS2 bit of the TQnOPT0 register, but only in the free-running mode.
Page 309 Chapter 8 16-Bit Timer/Event Counter Q Capture/compare register 3 (TQnCCR3) The TQnCCR3 register is a 16-bit register that has a capture function and a compare function. Whether this register is used as a capture register or a compare register can be specified by using the TQnCCS3 bit of the TQnOPT0 register, but only in the free-running mode.
Page 310 Chapter 8 16-Bit Timer/Event Counter Q Timer read buffer register (TQnCNT) The TQnCNT register is a timer read buffer register that can read 16-bit counter values. This register is read-only using a 16-bit memory manipulation instruction. RESET input sets this register to FFFFH. When TQnCE bit of TQnCTL0 register = 0, the hardware status is FFFFH, but a value of 0000H is returned when this register is read.
Page 311: Control Registers
Chapter 8 16-Bit Timer/Event Counter Q 8.4 Control Registers Timer Q0 control register 0 (TQnCTL0) Timer Q0 control register 0 is an 8-bit register that controls the operation of timer Q. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 312 Chapter 8 16-Bit Timer/Event Counter Q Timer Q control register 1 (TQnCTL1) The TQnCTL1 register is an 8-bit register that controls the operation of timer Q. This register can be read or written in 8-bit or 1-bit units. RESET input clears this register to 00H. Figure 8-8: Timer Q Control Register 1 (TQnCTL1) Format (1/2) After Symbol...
Page 313 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-8: Timer Q Control Register 1 (TQnCTL1) Format (2/2) TQnEEE Count clock selection Use the internal clock (clock selected with bits TQnCKS2 to TQnCKS0) Use the external clock from the TIQn0 input pin The valid edge when TQnEEE = 1 (use the external clock from TIQn0 pin) is specified with bits TQnEES1 and TQnEES0.
Page 314 Chapter 8 16-Bit Timer/Event Counter Q Timer Q dedicated I/O control register 0 (TQnIOC0) The TQnIOC0 register is an 8-bit register that controls the timer output. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Figure 8-9: Timer Q Dedicated I/O Control Register 0 (TQnIOC0) Format After Symbol...
Page 315 Chapter 8 16-Bit Timer/Event Counter Q Timer Q dedicated I/O control register 1 (TQnIOC1) The TQnIOC1 register is an 8-bit register that controls the valid edge of the external input signals (TIQn0 to TIQn3). This register can be read or written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 316 Chapter 8 16-Bit Timer/Event Counter Q Timer Q dedicated I/O control register 2 (TQnIOC2) The TQnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIQn0) and external trigger input signal (TIQn0). This register can be read or written in 8-bit or 1-bit units.
Page 317 Chapter 8 16-Bit Timer/Event Counter Q Timer Q option register 0 (TQnOPT0) The TQnOPT0 register is an 8-bit register that selects a capture or compare operation, and detects an overflow. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 318 Chapter 8 16-Bit Timer/Event Counter Q TIQnm pin noise elimination control register n (QnmNFC) The QnmNFC register is an 8-bit register that sets the digital noise filter of the timer Q input pin. This register can be read or written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 319: Operation
Chapter 8 16-Bit Timer/Event Counter Q 8.5 Operation Timer Q can perform the following operations. TQnEST TIQn0 TQnEEE Capture/ Compare Operation Software External Count clock Compare Write Write trigger input trigger input selection Interval timer mode Invalid Invalid Internal/TIQn0 pin Compare only Any time write External event counter...
Page 320 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-14: Flowchart of Basic Operation for Anytime Write START Initial setting Enable timer operation (TQnCE = 1) → Transfer values of TQnCCR0 to CCR0 buffer register Rewrite TQnCCR0 → Transfer to CCR0 buffer register Rewrite TQnCCR1 →...
Page 321 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-15: Timing Chart of Any Time Write TQnCE = 1 16-bit counter TQnCCR0 CCR0 buffer 0000H register INTTQnCC0 TQnCCR1 CCR1 buffer 0000H register INTTQnCC1 TQnCCR2 CCR2 buffer 0000H register INTTQnCC2 TQnCCR3 CCR3 buffer 0000H register INTTQnCC3...
Page 322 Chapter 8 16-Bit Timer/Event Counter Q Reload When data is written to the TQnCCRm register during timer operation, it is compared with the value of the 16-bit counter via the CCRm buffer register. The value of the TQnCCRm register can be rewritten when TQnCE = 1.
Page 323 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-17: Timing Chart of Reload TQnCE = 1 16-bit counter TQnCCR0 CCR0 buffer 0000H register Note Same value write TQnCCR1 CCR1 buffer 0000H register Note TQnCCR2 CCR2 buffer 0000H register TQnCCR3 CCR3 buffer 0000H register Note...
Page 324: Interval Timer Mode (Tqnmd2 To Tqnmd0 = 000)
Chapter 8 16-Bit Timer/Event Counter Q 8.5.2 Interval timer mode (TQnMD2 to TQnMD0 = 000) In the interval timer mode, an interrupt request signal (INTTQnCC0) is generated when the set value of the TQnCCR0 register matches the value of the 16-bit counter, and the 16-bit counter is cleared. Rewriting the TQnCCRm register is enabled when TQnCE = 1.
Page 325 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-19: Basic Operation Timing in Interval Timer Mode (1/2) (a) When only TQnCCR0 register value is rewritten and TOQnm is not output TQnCE = 1 FFFFH 16-bit counter TQnCCR0 CCR0 buffer 0000H register TQnCCR1 CCR1 buffer 0000H...
Page 326 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-19: Basic Operation Timing in Interval Timer Mode (2/2) (b) When D01 = D31, only TQnCCR1 register value is rewritten, and TOQnm is output TQnCE = 1 FFFFH 16-bit counter TQnCCR0 CCR0 buffer 0000H register TQnCCR1...
Page 327: External Event Counter Mode (Tqnmd2 To Tqnmd0 = 001)
Chapter 8 16-Bit Timer/Event Counter Q 8.5.3 External event counter mode (TQnMD2 to TQnMD0 = 001) In the external event count mode, the external event count input (TIQn0 pin input) is used as a count-up signal. Regardless of the setting of the TQnEEE bit of the TQnCTL0 register, 16-bit timer/event counter Q counts up the external event count input (TIQn0 pin input) when it is set in the external event count mode.
Page 328 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-20: Flowchart of Basic Operation in External Event Counter Mode START Initial setting • Set external event count mode (TQnCTL0: TQnMD2 to TQnMD0 = Note 1 001) • Set valid edge (TQnIOC2: TQnEES1, TQnEES0).
Page 329 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-21: Basic Operation Timing in External Event Counter Mode (1/2) (a) When only TQnCCR0 register value is rewritten and TOQnm is not output TQnCE = 1 FFFFH 16-bit counter TQnCCR0 CCR0 buffer 0000H register TQnCCR1 CCR1 buffer...
Page 330 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-21: Basic Operation Timing in External Event Counter Mode (2/2) (b) When D01 = D31, only TQnCCR1 register is rewritten, and TOQnm is output TQnCE = 1 FFFFH 16-bit counter TQnCCR0 CCR0 buffer 0000H register TQnCCR1...
Page 331: External Trigger Pulse Mode (Tqnmd2 To Tqnmd0 = 010)
Chapter 8 16-Bit Timer/Event Counter Q 8.5.4 External trigger pulse mode (TQnMD2 to TQnMD0 = 010) When TQnCE = 1 in the external trigger pulse mode, the 16-bit counter stops at FFFFH and waits for input of an external trigger (TIQn0 pin input). When the counter detects the edge of the external trigger (TIQn0 pin input), it starts counting up.
Page 332 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-22: Flowchart of Basic Operation in External Trigger Pulse Output Mode START Initial setting • Select clock. (TQnCTL1: TQnEEE = 0) (TQnCTL0: TQnCKS2 to TQnCKS0) • Set external trigger pulse output mode. External trigger (TIQn0 pin) input (TQnCTL1: TQnMD2 to TQnMD0 = 010) •...
Page 333 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-23: Basic Operation Timing in External Trigger Pulse Output Mode TQnCE = 1 FFFFH 16-bit counter External trigger (TIQ00 pin) TQnCCR0 CCR0 buffer 0000H register TQnCCR1 CCR1 buffer 0000H register TQnCCR2 CCR2 buffer 0000H register TQnCCR3...
Page 334: One-Shot Pulse Mode (Tqnmd2 To Tqnmd0 = 011)
Chapter 8 16-Bit Timer/Event Counter Q 8.5.5 One-shot pulse mode (TQnMD2 to TQnMD0 = 011) When TQnCE is set to 1 in the one-shot pulse mode, the 16-bit counter waits for the setting of the TQnEST bit (to 1) or a trigger that is input when the edge of the TIQn0 pin is detected, while holding FFFFH.
Page 335 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-24: Flowchart of Basic Operation in One-Shot Pulse Mode START Initial setting • Select clock. (TQnCTL1: TQnEEE = 0) (TQnCTL0: TQnCKS2 to TQnCKS0) • Set one-shot pulse mode. (TQnCTL1: TQnMD2 to TQnMD0 = 011) •...
Page 336 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-25: Timing of Basic Operation in One-Shot Pulse Mode TQnCE = 1 TQnEST = 1 FFFFH Note 16-bit counter External trigger (TIQn0 pin) TQnCCR0 CCR0 buffer 0000H register TQnCCR1 CCR1 buffer 0000H register TQnCCR2 CCR2 buffer 0000H...
Page 337: Pwm Mode (Tqnmd2 To Tqnmd0 = 110)
Chapter 8 16-Bit Timer/Event Counter Q 8.5.6 PWM mode (TQnMD2 to TQnMD0 = 110) In the PWM mode, TMQn capture/compare register k (TQnCCRk) is used to set the duty factor and TMQn capture/compare register 0 (TQnCCR0) is used to set the cycle. By using these two registers and operating the timer, variable-duty PWM is output.
Page 338 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-26: Flowchart of Basic Operation in PWM Mode (1/2) (a) When values of TQnCCRm register is not rewritten during timer operation START Initial setting • Select clock. (TQnCTL0: TQnCKS2 to TQnCKS0) • Set PWM mode. (TQnCTL1: TQnMD2 to TQnMD0 = 100) •...
Page 339 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-26: Flowchart of Basic Operation in PWM Mode (2/2) (b) Value of TQnCCRm register rewritten during timer operation START Initial setting • Select clock. (TQnCTL0: TQnCKS2 to TQnCKS0) • Set PWM mode. (TQnCTL1: TQnMD2 to TQnMD0 = 100) •...
Page 340 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-27: Basic Operation Timing in PWM Mode (1/2) (a) When rewriting values of TQnCCR1 to TQnCCR3 registers TQnCE = 1 FFFFH 16-bit counter TQnCCR0 CCR0 buffer 0000H register Same value write TQnCCR1 CCR1 buffer 0000H register TQnCCR2...
Page 341 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-27: Basic Operation Timing in PWM Mode (2/2) (b) When rewriting values of TQnCCR0 to TQnCCR3 registers TQnCE = 1 FFFFH 16-bit counter TQnCCR0 CCR0 buffer 0000H register Same value write TQnCCR1 CCR1 buffer 0000H register TQnCCR2...
Page 342: Free-Running Mode (Tqnmd2 To Tqnmd0 = 101)
Chapter 8 16-Bit Timer/Event Counter Q 8.5.7 Free-running mode (TQnMD2 to TQnMD0 = 101) In the free-running mode, both the interval function and the compare function can be realized by operating the 16-bit counter as a free-running counter and selecting capture/compare operation with the TQnCCS3 to TQnCCS0 bits of the TQnOPT0 register.
Page 343 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-28: Flowchart of Basic Operation in Free-Running Mode START Initial setting • Select clock. (TQnCTL0: TQnCKS2 to TQnCKS0) • Set free-running mode. (TQnCTL1: TQnMD2 to TQnMD0 = 101) Set TQnCCSm. TQnCCSm = 0 TQnCCSm = 1 (Compare) (Capture)
Page 344 Chapter 8 16-Bit Timer/Event Counter Q When TQnCCSn = 0 setting (compare function) When TQnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH, and continues counting up in the free-running mode until TQnCE is cleared to 0. If a value is written to the TQnCCRm register in this mode, it is transferred to the CCRm buffer registers (anytime write).
Page 345 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-29: Basic Operation Timing in Free-Running Mode (1/4) (a) (TQnCCS3 = 0, TQnCCS2 = 0, TQnCCS1 = 0, TQnCCS0 = 0) TQnCE = 1 FFFFH 16-bit counter TQnCCR0 CCR0 buffer 0000H register INTTQnCC0 match interrupt TOQn0 TQnCCR1...
Page 346 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-29: Basic Operation Timing in Free-Running Mode (2/4) (b) (TQnCCS3 = 1, TQnCCS2 = 1, TQnCCS1 = 1, TQnCCS0 = 1) TQnCE = 1 FFFFH 16-bit counter TIQn0 TQnCCR0 0000H INTTQnCC0 capture interrupt TIQn1 TQnCCR1 0000H...
Page 347 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-29: Basic Operation Timing in Free-Running Mode (3/4) (c) (TQnCCS3 = 1, TQnCCS2 = 1, TQnCCS1 = 1, TQnCCS0 = 0) TQnCE = 1 FFFFH 16-bit counter TIQn0 INTTQnCC0 0000H INTTQnCC0 capture interrupt TIQn1 TQnCCR1 0000H...
Page 348 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-29: Basic Operation Timing in Free-Running Mode /4/4) (d) (TQnCCS3 = 0, TQnCCS2 = 1, TQnCCS1 = 0, TQnCCS0 = 1) TQnCE = 1 FFFFH 16-bit counter TIQn0 TQnCCR0 0000H INTTQnCC0 capture interrupt TQnCCR1 CCR1 buffer 0000H...
Page 349: Pulse Width Measurement Mode (Tqnmd2 To Tqnmd0 = 110)
Chapter 8 16-Bit Timer/Event Counter Q 8.5.8 Pulse width measurement mode (TQnMD2 to TQnMD0 = 110) In the pulse width measurement mode, free-running counting is performed. The value of the 16-bit counter is captured to capture register m (TQnCCRm) when both the rising and falling edges of the TIQnm pin are detected, and the 16-bit counter is cleared to 0000H.
Page 350 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-31: Basic Operation Timing in Pulse Width Measurement Mode TQnCE = 1 FFFFH FFFFH 16-bit counter TIQn0 TQnCCR0 0000H INTTQnCC0 Cleared by writing 0 TQnOVF from CPU INTTQnOV Remarks: 1. D00, D01, D02, D03: Values captured to TQnCCR0 register (0000H to FFFFH) 2.
Page 351: Timer Synchronization Operation Function
Timer P and timer Q have a timer synchronized operation function (tuned operation mode). The timers that can be synchronized are listed in Table 8-3 (√ : Settable, ×: Not settable). Table 8-3: Tuned Operation Mode of Timer Master Timer Slave Timer V850E/RS1 √ TMP0 TMP1 √...
Page 352: Table 8-5: Timer Output Functions
Chapter 8 16-Bit Timer/Event Counter Q Table 8-5: Timer Output Functions Free-Running Mode PWM Mode Triangular Wave PWM Mode Tuned Timer Channel Tuning OFF Tuning ON Tuning OFF Tuning ON Tuning OFF Tuning ON ← ← ← TOP00 Toggle TMP0 ←...
Page 353 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-32: Tuned Operation Image (TMP2, TMP3, TMQ0) Unit operation Tuned operation TMP2 TMP2 (master ) + TMP3 (slave) + TMQ0 (slave) 16-bit timer/counter 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare TOP21 (PWM output) 16-bit capture/compare TOP21 (PWM output) 16-bit capture/compare...
Page 354 Chapter 8 16-Bit Timer/Event Counter Q Figure 8-33: Basic Operation Timing of Tuned PWM Function (TMP2, TMP3, TMQ0) FFFFH TMP2 16-bit counter 0000H TP2CE TP3CE TQ0CE TP2CCR0 TP2CCR1 TP3CCR0 TP3CCR1 TQ0CCR0 TQ0CCR1 TQ0CCR2 TQ0CCR3 INTTP2CC0 match interrupt INTTP2CC1 match interrupt INTTP3CC0 match interrupt INTTP3CC1...
Page 355: Chapter 9 16-Bit Interval Timer M
Chapter 9 16-Bit Interval Timer M The V850E/RS1 includes one 16-bit interval timer M (TMM0) 9.1 Features Timer M (TMM0) supports only a clear & start mode. It does not support a free-running mode. To use timer M in a manner equivalent to in the free-running mode, set the compare register to FFFFH and start the 16-bit counter.
Page 356: Configuration
Chapter 9 16-Bit Interval Timer M 9.2 Configuration TMM0 includes the following hardware. Table 9-1: Configuration of TMM Item Configuration Timer register 16-bit counter Register TMM0 compare register 0 (TM0CMP0) Control register TMM0 timer control register (TM0CTL0) Figure 9-1: Block Diagram of TMM0 Internal bus TM0CTL0 TM0CE TM0CKS2 TM0CKS1TM0CKS0...
Page 357: Control Register
Chapter 9 16-Bit Interval Timer M 9.3 Control Register TMM0 timer control register (TM0CTL0) The TMM0 timer control register (TM0CTL0) is an 8-bit register used to control the timer operation. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 358: Operation
Chapter 9 16-Bit Interval Timer M 9.4 Operation 9.4.1 Interval timer mode In the interval timer mode, a match interrupt signal (INTTM0EQ0) is output when the value of the 16-bit counter matches the value of TMM0 compare register 0 (TM0CMP0). At the same time, the counter is cleared to 0000H and starts counting up.
Page 359: Chapter 10 Functions Of Watchdog Timer 2
Chapter 10 Functions of Watchdog Timer 2 10.1 Functions Watchdog Timer 2 has the following functions. Note 1 • Default start Watchdog timer Reset mode: Reset operation upon overflow of Watchdog timer 2 (generation of WDT2RES signal) Non-maskable interrupt request mode: NMI operation upon overflow of Watchdog timer 2 Note 2 (generation of INTWDT2 signal) •...
Page 360: Configuration
Chapter 10 Functions of Watchdog Timer 2 10.2 Configuration Watchdog Timer 2 consists of the following hardware. Table 10-1: Configuration of Watchdog Timer 2 Item Configuration Oscillation stabilization time select register (OSTS) Control registers Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE) 10.3 Control Registers Oscillation stabilization time select register (OSTS)
Page 361 Chapter 10 Functions of Watchdog Timer 2 Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of Watchdog timer 2. This register can be read or written in 8-bit or 1-bit units. This register can be read any number of times, but it can be written only once following reset release.
Page 362: Table 10-2: Watchdog Timer 2 Clock Selection
Chapter 10 Functions of Watchdog Timer 2 Table 10-2: Watchdog Timer 2 Clock Selection Selected WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 100 kHz (MIN.) 200 kHz (TYP.) 400 kHz (MAX.) clock 41.0 ms 20.5 ms 10.2 ms 81.9 ms 41.0 ms 20.5 ms 163.8 ms 81.9 ms...
Page 363 Chapter 10 Functions of Watchdog Timer 2 Watchdog timer enable register (WDTE) The counter of the Watchdog timer is cleared and counting restarted by writing “ACH” to WDTE. WDTE is set by an 8-bit memory manipulation instruction. RESET Input sets this register to 9AH. Figure 10-4: Watchdog Timer Enable Register (WDTE) Format Symbol Address...
Page 364: Operation
Chapter 10 Functions of Watchdog Timer 2 10.4 Operation Oscillation stabilization time selection function The wait time until the oscillation stabilizes after the software STOP mode is released is controlled by the OSTS register. The OSTS register can be read or written 8-bit units. RESET input sets this register to 03H.
Page 365 Chapter 10 Functions of Watchdog Timer 2 Operation as Watchdog timer 2 Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset using byte access. To use Watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction.
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Page 367: Chapter 11 A/D Converter
Chapter 11 A/D Converter 11.1 Functions The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 16 channels of analog input signals (ANI0 to ANI15). The A/D converter has the following features. •...
Page 368 Chapter 11 A/D Converter The block diagram of the A/D converter is shown below. Figure 11-1: Block Diagram of A/D Converter REF0 ADSCM1H.PDB bit Sample & hold circuit ANI0 ANI1 Voltage ANI2 comparator ADSCM1H.PDB bit ANI15 REF0 ADVSM0.VMSEN bit ADSCM0H.CE bit SELCNT1 INTAD ADTRG...
Page 369: Configuration
Chapter 11 A/D Converter 11.2 Configuration The A/D converter includes the following hardware. Table 11-1: Configuration of A/D Converter Item Configuration Analog inputs 16 channels (ANI0 to ANI15) Successive approximation register (SAR) Registers A/D conversion result registers 0 – 15 (ADA0CRn) A/D diagnostic mode conversion result registers (ADA0CRDD, ADA0CRSS) A/D converter mode registers 0 to 1 (ADSCM0H, ADSCM0L, ADSCM1H) Control registers...
Page 370 Chapter 11 A/D Converter ANI0 to ANI15 pins These are analog input pins for the 16 channels of the A/D converter and are used to input analog signals to be converted into digital signals. Pins other than the one selected as analog input with the analog input channel specification register (ADSCM0 ) can be used as input port pins.
Page 371: Control Registers
Chapter 11 A/D Converter 11.3 Control Registers The A/D converter is controlled by the following registers. • A/D conversion result register n (ADA0CRn, ADA0CRDD, ADA0CRSS) • A/D converter mode registers 0, 1 (ADSCM0H, ADSCM0L, ADSCM1H) • A/D converter extended mode control register 0 (ADVMS0) •...
Page 372 Chapter 11 A/D Converter Figure 11-2: A/D Conversion Result Register n (ADA0CRn, ADA0CRDD, ADA0CRSS) Format (2/2) (b) After RESET: ADA0CRDD, ADA0CRSS = 0000H, Read only registers Symbol Address ADA0CRDD AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFFFF240H ADA0CRSS AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFFFF242H The relationship between the analog voltage input to an analog input pin (ANI0 to ANI15) and the value...
Page 373 Chapter 11 A/D Converter Figure 11-3: Relationship Between Analog Input Voltages and A/D Converter Results 1023 1022 A/D conversion result 1021 (ADA0CRn) 2043 1022 2045 1023 2047 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 Input voltage/AV REF0 Remark: n = 0 to 15...
Page 374 Chapter 11 A/D Converter A/D converter mode register 0H (ADSCM0H) This is an 8-bit register used to specify the operating mode and to control conversion operation. This register is accessed with an 8-bit or an 1-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 11-4: A/D Converter Mode Register 0H (ADSCM0H) Format Symbol Address...
Page 375 Chapter 11 A/D Converter A/D converter mode register 0L (ADSCM0L) This is an 8-bit register used to specify the analog input channel(s) for conversion. This register is set with an 8-bit or an 1-bit memory manipulation instruction. RESET input clears this bit to 00H. Figure 11-5: A/D Converter Mode Register 0L (ADSCM0L) Format (1/2) Symbol Address...
Page 376 Chapter 11 A/D Converter Figure 11-5: A/D Converter Mode Register 0L (ADSCM0L) Format (2/2) Analog input channel selector ANIS ADVMS0.DIAGEN=”0” ADVMS0.DIAGEN=”1” Scan mode conver- Scan mode conversion end chan- Select mode Select mode 3 2 1 0 sion end channel nel, including Diagnostic Function (ADSCM0H.MS=1) (ADSCM0H.MS=1)
Page 377 Chapter 11 A/D Converter AD converter mode register 1H (ADSCM1H) This register is used to control the power supply to the AD converter and also set the conversion time. RESET input clears this register to 00H. Figure 11-6: AD Converter Mode Register 1H (ADSCM1H) Format Symbol Address After reset...
Page 378 Chapter 11 A/D Converter A/D discharge and diagnostic mode register (ADVMS0) This register is used to select the extended mode operation of the AD converter. RESET input clears this register to 01H. Figure 11-7: AD Converter Extended Mode Register (ADVMS0) Symbol Address After reset...
Page 379 Chapter 11 A/D Converter AD converter external trigger selection register (SELCNT1) This register is used to select the external source for the conversion start trigger. RESET input clears this register to 00H. Figure 11-8: AD Converter External Trigger Selection Register (SELCNT1) Format Symbol Address After reset...
Page 380: Operation
Chapter 11 A/D Converter 11.4 Operation 11.4.1 Basic operation Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADSCM0H, ADSCM0L, ADSCM1H, and ADVMS0 registers. When the CE bit of the ADSCM0H register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger.
Page 381: Trigger Mode
Chapter 11 A/D Converter 11.4.2 Trigger mode Several conversion operations can be specified for A/D converter by specifying operation modes and trigger modes. Those modes are set using bits PLM, TRG0 and TRG1 of A/D conversion mode register 0 (ADSCM0H). There are two trigger modes, the software trigger mode and the external trigger mode.
Page 382 Chapter 11 A/D Converter Software trigger mode The following trigger modes that serve as the start timing of A/D conversion processing are available: A/D trigger mode and polling mode. These trigger modes are set using the ADSCM0H register. (a) A/D trigger mode In this mode, the A/D conversion is started by setting bit CE of A/D conversion mode register 0 (ADSCM0H) to 1.
Page 383: Operation Mode
Chapter 11 A/D Converter 11.4.3 Operation mode Four operation modes are described below. The operation modes are set with bits MS and PLM of the ADSCM0H register (refer to 11.3 ”Control Registers” on page 371). Select mode In this mode, a single A/D conversion of one analog input specified with bits ANIS3 - ANIS00 of the ADSCM0L register is performed.
Page 384 Chapter 11 A/D Converter Figure 11-10: Example of Select Mode Operation (ANI2) (2/2) (b) Block diagram Example Analog Input ADA0CRn ADSCM0H ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 ADA0CR3 ANI4 ADA0CR4 ANI5 ADA0CR5 ANI6 ADA0CR6 ANI7 ADA0CR7 ANI8 ADA0CR8 ANI9 ADA0CR9 converter ANI10...
Page 385 Chapter 11 A/D Converter Single scan mode In this mode, sequential A/D conversion of the selected analog input channels specified with the SANI3 - SANI0 and ANIS3 - ANIS0 bits of the ADSCM0L register is performed. The conversion result for the selected analog inputs is saved to the ADA0CRn registers. A/D conversion starts upon detection of a trigger, the selected analog inputs are operated in sequence, and A/D conversion interrupt (INTAD) is output upon conversion completion of the final analog input channel.
Page 386 Chapter 11 A/D Converter Figure 11-11: Example of Single Scan Mode Operation (4-Channel Scan (ANI2 to ANI5)) (2/2) (b) Block diagram Example Analog Input ADA0CRn ADSCM0H ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 ADA0CR3 ANI4 ADA0CR4 ANI5 ADA0CR5 ANI6 ADA0CR6 ANI7 ADA0CR7 ANI8...
Page 387 Chapter 11 A/D Converter Continuous select mode (Polling mode) In this mode, continuous A/D conversion of one analog input specified with the ADSCM0L register is performed. The conversion result for that analog input is saved to the ADA0CRn register. A/D conversion starts upon detection of a trigger, an A/D conversion interrupt (INTAD) is output upon each conversion completion, and A/D conversion is then started again unless CE bit of ADSCM0H register is set to 0.
Page 388 Chapter 11 A/D Converter Figure 11-12: Example of Continuous Select Mode Operation (ANI2) (2/2) (b) Block diagram Example Analog Input ADA0CRn ADSCM0H ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 ADA0CR3 ANI4 ADA0CR4 ANI5 ADA0CR5 ANI6 ADA0CR6 ANI7 ADA0CR7 ANI8 ADA0CR8 ANI9 ADA0CR9 converter...
Page 389 Chapter 11 A/D Converter Continuous scan mode (Polling mode) In this mode, A/D conversion is performed starting from ANI2 up to ANI5 specified by the ADSCM0L register. The A/D conversion result is saved to the ADA0CRn register corresponding to each analog input. A/D conversion starts from ANI0 upon trigger detection, an A/D conversion interrupt (INTAD) is generated when conversion of the specified analog input ends, and A/D conversion from ANI0 starts again.
Page 390 Chapter 11 A/D Converter Figure 11-13: Example of Continuous Scan Mode Operation (ANI2 to ANI5) (2/2) (b) Block diagram Example Analog Input ADA0CRn ADSCM0H ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 ADA0CR3 ANI4 ADA0CR4 ANI5 ADA0CR5 ANI6 ADA0CR6 ANI7 ADA0CR7 ANI8 ADA0CR8 ANI9...
Page 391: Extended Functions
Chapter 11 A/D Converter 11.5 Extended Functions 11.5.1 Automatic discharge operation The automatic discharge operation internally connects the sample and hold circuit to GND in order to catch open analog inputs and other failure modes. This function is disabled by default and is controlled by the ADVMS0 register (refer to 11.3 ”Control Registers”...
Page 392: Precautions On Operation
Chapter 11 A/D Converter 11.6 Precautions on Operation 11.6.1 Stopping A/D If 0 is written in the CE bit of the ADSCM0H register during A/D conversion operation, it stops A/D conversion operation and an A/D conversion result is not stored in the ADACRn register (n = 0 to 15).
Page 393: Compare Match Interrupt In Timer Trigger Mode (External Trigger Mode)
Chapter 11 A/D Converter 11.6.5 Compare match interrupt in timer trigger mode (External trigger mode) A TMP2 timer P2 capture/compare registers 0, 1 (TP2CCR0, TP2CCR1) underflow interrupt (INTTP2CC1 or INTTP2CC0) is an A/D conversion start trigger that starts conversion operation. At this time, the TP2CCR0 or TP2CCR1 match interrupt (INTTP2CC1 or INTTP2CC0) also functions as a compare register match interrupt for the CPU.
Page 394 Chapter 11 A/D Converter Figure 11-15: Conversion Result Read Timing (When Conversion Result Is Normal) A/D conversion end ADA0CRn Normal conversion result INTAD CE bit of ADSCM0H A/D operation Normal conversion result read stopped Remark: n = 0 to 15 User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com...
Page 395: Cautions
Chapter 11 A/D Converter 11.7 Cautions When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the CE bit of the ADSCM0H register and PDB bit of the ADSCM1H register to 0. Input range of ANI0 to ANI15 pins Input the voltage within the specified range to the ANI0 to ANI15 pins.
Page 396 Chapter 11 A/D Converter Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADSCM0L register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADSCM0L register is rewritten.
Page 397 Chapter 11 A/D Converter REF0 (a) The AV pin is used as the power supply pin of the A/D converter and also supplies power REF0 to the alternate-function ports. In an application where a backup power supply is used, be sure to supply the same voltage as V to the AV pin as shown in Figure 11-18.
Page 398: How To Read A/D Converter Characteristics Table
Chapter 11 A/D Converter 11.8 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 399 Chapter 11 A/D Converter Quantization error This is an error of 1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of 1/2 LSB into the same digital codes, a quantization error is unavoidable.
Page 400 Chapter 11 A/D Converter Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 0…111 (full scale 3/2 LSB). Figure 11-22: Full-Scale Error Full-scale error REF0 - REF0 - REF0 -...
Page 401 Chapter 11 A/D Converter Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. Figure 11-24: Integral Linearity Error 1 ..
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Page 403: Chapter 12 Asynchronous Serial Interface A (Uarta)
Chapter 12 Asynchronous Serial Interface A (UARTA) The V850E/RS1 includes two asynchronous serial interfaces A (UARTA). 12.1 Features • Transfer rate: 300 bps to 312.5 kbps • Full-duplex communication: • UARTA receive data register n (UAnRX) • UARTA transmit data register n (UAnTX) •...
Page 404: Configuration
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.2 Configuration UARTA consists of the following hardware: Table 12-1: Configuration of UARTA0 and UARTA1 Item Configuration UARTAn reception shift register UARTAn reception data register (UAnRX) Register UARTAn transmit shift register UARTAn transmit data register (UAnTX) Reception data input 2 (RXDA0, RXDA1) Transmit data output...
Page 405 Chapter 12 Asynchronous Serial Interface A (UARTA) Figure 12-1: Block Diagram of Asynchronous Serial Interface A Internal bus INTUAnT INTUAnR Transmission Reception unit UAnTX UAnRX unit Receive Transmit Transmission Reception shift register shift register controller controller Filter Baud rate Baud rate TXDAn Selector generator...
Page 406: Control Registers
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.2.1 Control registers UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that specifies the operation of the asynchronous serial interface. UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the input clock of the asynchronous serial interface.
Page 407: Control Registers
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.3 Control Registers UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the serial transfer operation of UARTAn. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 10H.
Page 408 Chapter 12 Asynchronous Serial Interface A (UARTA) Figure 12-2: UARTAn Control Register 0 (UAnCTL0) Format (2/2) UAnDIR Selection of transfer direction mode (MSB/LSB) MSB first LSB first This bit can be rewritten only when the UAnPWR bit = 0 or when UAnTXE bit = UAnRXE bit = 0. UAnPS1 UAnPS0 Selection of parity for transmission...
Page 409 Chapter 12 Asynchronous Serial Interface A (UARTA) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the clock of UARTAn. This register can be read or written in 8-bit units only. Reset input clears this register to 00H. Figure 12-3: UARTAn Control Register 1 (UAnCTL1) Format Address: UA0CTL1: FFFFFA01H, UA1CTL1: FFFFFA11H Symbol...
Page 410 Chapter 12 Asynchronous Serial Interface A (UARTA) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is used to select the baud rate (serial transfer rate) clock of UARTAn. This register can be read or written in 8-bit units. Reset input sets this register to FFH. Figure 12-4: UARTAn Control Register 2 (UAnCTL2) Format Address: UA0CTL2: FFFFFA02H, UA1CTL2: FFFFFA12H After...
Page 411 Chapter 12 Asynchronous Serial Interface A (UARTA) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of UARTAn. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 14H.
Page 412 Chapter 12 Asynchronous Serial Interface A (UARTA) UARTAn status register (UAnSTR) The UAnSTR register is an 8-bit register that indicates the transfer status of UARTAn and the con- tents of a reception error. This bit can be read or written in 8-bit or 1-bit units, but the UAnTSF bit can only be read. The UAnPE, UAnFE, and UAnOVE bits can be read or written, but they can only be cleared by writing 0 to them, and cannot be set by writing 1 (if 1 is written to these bits, they hold the current status).
Page 413 Chapter 12 Asynchronous Serial Interface A (UARTA) Figure 12-6: UARTAn Status Register (UAnSTR) Format (2/2) UAnFE Framing error flag • When UAnPWR bit of UAnCTL0 register = 0 or when UAnRXE bit of UAnCTL0 register = 0 • When 0 is written When a stop bit is not detected on reception •...
Page 414 Chapter 12 Asynchronous Serial Interface A (UARTA) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores the parallel data converted by the receive shift register. On completion of reception of 1 byte of data, the data stored in the receive shift register is trans- ferred to the UAnRX register.
Page 415: Interrupt Request Signals
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.4 Interrupt Request Signals UARTAn generates the following two types of interrupt request signals. • Reception complete interrupt request signal (INTUAnR) • Transmission enable interrupt request signal (INTUAnT) Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower.
Page 416: Operation
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.5 Operation 12.5.1 Data format Full-duplex serial data is transmitted or received. The transmit/receive data is in the format shown in Figure 12-9, consisting of a start bit, character bits, a parity bit, and 1 or 2 stop bits. The character bit length in one data frame, parity, stop bit length, and whether data is transferred with the MSB or LSB first, are specified by the UAnCTL0 register.
Page 417: Uart Transmission
Chapter 12 Asynchronous Serial Interface A (UARTA) Figure 12-9: Format of Transmit/Receive Data of UARTA (2/2) (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start Parity Stop Stop (e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H 1 data frame Start Stop...
Page 418: Procedure Of Continuous Transmission
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.5.3 Procedure of continuous transmission With UARTA, the next transmit data can be written to the UAnTX register as soon as the UARTAn trans- mit shift register has started its shift operation. The timing at which data is transferred to the UARTAn transmit shift register can be identified by the transmission enable interrupt request signal (INTUAnT).
Page 419 Chapter 12 Asynchronous Serial Interface A (UARTA) Figure 12-12: Timing of Continuous Transmission Operation (a) Start of transfer Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn UAnTX Data (1) Data (2) Data (3) Transmit Data (2) shift Data (1) register...
Page 420: Uart Reception
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.5.4 UART reception When the UAnPWR bit of the UAnCTL0 register is set to 1 and then the UAnRX bit of the UAnCTL0 reg- ister is set to 1, UARTA waits for reception. In the reception wait status, the RXDAn pin is monitored and the start bit is detected.
Page 421: Reception Errors
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.5.5 Reception errors Reception errors are classified into three types: parity errors, framing errors, and overrun errors. As a result of receiving data, an error flag is set in the UAnSTR register, and a reception complete interrupt request signal (INTUAnR) is generated.
Page 422 Chapter 12 Asynchronous Serial Interface A (UARTA) When a reception errors occur, perform the following procedures depending upon the type of error: • Parity error If false data is received due to problems such as noise in the reception line, discard the received data and retransmit.
Page 423: Types And Operation Of Parity
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.5.6 Types and operation of parity The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission side and reception side. Even parity and odd parity can be used to detect a “1”...
Page 424: Noise Filter Of Receive Data
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.5.7 Noise filter of receive data The RXDAn pin is sampled using the UART internal clock (f XCLK If the sampled value is the same twice in a row, the output of the match detector changes, and the sig- nal on the RXDAn pin is sampled as input data.
Page 425: Dedicated Baud Rate Generator
Chapter 12 Asynchronous Serial Interface A (UARTA) 12.6 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector and 8-bit programmable counters, and generates a serial clock for transmission/reception by UARTAn. The output of the dedi- cated baud rate generator can be selected as the serial clock on a channel by channel basis.
Page 426 Chapter 12 Asynchronous Serial Interface A (UARTA) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is used to select the clock for UARTAn. For details, refer to 12.3 (2) UARTAn control register 1 (UAnCTL1). UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is used to select the baud rate (serial transfer rate) clock for UARTAn. For details, refer to 12.3 (3) UARTAn control register 2 (UAnCTL2).
Page 427: Table 12-5: Baud Rate Generator Set Data
Chapter 12 Asynchronous Serial Interface A (UARTA) Example of baud rate setting Table 12-5: Baud Rate Generator Set Data = 40 MHz = 32 MHz = 24 MHz Baud Rate (bps) UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%) 0.16 0.16 0.16...
Page 428 Chapter 12 Asynchronous Serial Interface A (UARTA) Permissible baud rate range for reception The permissible baud rate error during reception is shown below. Caution: Be sure to set the baud rate error for reception to within the permissible error range, by using the expressions shown below.
Page 429: Table 12-6: Permissible Maximum/Minimum Baud Rate Error
Chapter 12 Asynchronous Serial Interface A (UARTA) Therefore, the maximum receivable baud rate on the transmission side is as follows. BRmax = (FLmin/11) Brate 21k + 2 Similarly, the permissible maximum transfer rate can be calculated as follows. k + 2 21k- 2 ×...
Page 430: Caution For Use In On-Chip Debug Mode
Chapter 12 Asynchronous Serial Interface A (UARTA) Transfer rate for continuous transmission The transfer rate from the stop bit to the start bit of the next data is extended two clocks when con- tinuous transmission is executed. However, the timing on the reception side is initialized when the start bit is detected, and therefore, the transfer result is not affected.
Page 431: Chapter 13 3-Wire Serial Interface (Csib)
Chapter 13 3-Wire Serial Interface (CSIB) The V850E/RS1 includes two 3-wire serial interfaces (CSIB). 13.1 Features • Master mode and slave mode selectable • 3-wire serial interface for 8-bit to 16-bit transfer • Interrupt request signals (INTCBnT and INTCBnR) •...
Page 432: Table 13-2: List Of 3-Wire Serial Interface Pins
Chapter 13 3-Wire Serial Interface (CSIB) The pins of the 3-wire serial interface (CSIB) function alternately as port pins. For how to select the alternate function, refer to the descriptions of the registers in Chapter 4 ”Port Functions” on page 105. Table 13-2: List of 3-Wire Serial Interface Pins Pin Name Alternate-Function Pin Function...
Page 433: Control Registers Overview
Chapter 13 3-Wire Serial Interface (CSIB) 13.3 Control Registers Overview CSIBn control register 0 (CBnCTL0) The CBnCTL0 register is an 8-bit register that specifies the operation of the 3-wire serial interface. CSIBn control register 1 (CBnCTL1) The CBnCTL1 register is an 8-bit register that selects the transmission/reception timing and input clock of the 3-wire serial interface.
Page 434: Control Registers Description
Chapter 13 3-Wire Serial Interface (CSIB) 13.4 Control Registers Description CSIBn control register 0 (CBnCTL0) This register controls the serial transfer operation of CSIB. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 01H. Figure 13-2: CSIBn Control Register 0 (CBnCTL0) Format (1/2) Address: CB0CTL0: FFFFFD00H, CB1CTL0: FFFFFD10H After...
Page 435 Chapter 13 3-Wire Serial Interface (CSIB) Figure 13-2: CSIBn Control Register 0 (CBnCTL0) Format (2/2) Note Specification of transfer mode CBnTMS Single transfer mode Continuous transfer mode When the CBnTMS bit = 0, the single transfer mode is set in which continuous transmission/reception is not sup- ported.
Page 436 Chapter 13 3-Wire Serial Interface (CSIB) CSIBn control register 1 (CBnCTL1) This is an 8-bit register that selects the transmission/reception timing and input clock of CSIBn. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Caution: The CBnCTL1 register can be rewritten only when the CBnPWR bit of the CBnCTL0 register is 0.
Page 437 Chapter 13 3-Wire Serial Interface (CSIB) Figure 13-3: CSIBn Control Register 1 (CBnCTL1) Format (2/2) Input clock CBnCKS2 CBnCKS1 CBnCKS0 Mode n = 0 n = 1 Master mode Master mode Master mode Master mode Master mode Master mode Note TMP0 (TOP01) Master mode External clock (SCKBn)
Page 438 Chapter 13 3-Wire Serial Interface (CSIB) CSIBn control register 2 (CBnCTL2) This is an 8-bit register that controls the number of serial transfer bits of CSIB. It can be read or written in 8-bit units. Reset input clears this register to 00H. Caution: The CBnCTL2 register can be rewritten when the CBnPWR bit of the CBnCTL0 regis- ter = 0 or when the CB0TXE and CB0RXE bits = 0.
Page 439 Chapter 13 3-Wire Serial Interface (CSIB) CSIBn status register (CBnSTR) This is an 8-bit register that indicates the status of CSIB. Although this register can be read or written in 8-bit or 1-bit units, the CBnSTF flag is read-only. Reset input clears this register to 00H. Clearing the CBnPWR bit of the CBnCTL0 register to 0 also initializes this register.
Page 440 Chapter 13 3-Wire Serial Interface (CSIB) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. If reception is enabled, a reception operation is started when the CBnRX register is read. If the transfer data length is 8 bits, the lower 8 bits of the CBnRX register are read-only in 8-bit units as the CBnRXL register.
Page 441: Transfer Data Length Change Function
Chapter 13 3-Wire Serial Interface (CSIB) 13.5 Transfer Data Length Change Function The transfer data length of CSIB can be changed from 8 to 16 bits in 1-bit units by using the CBnCL3 to CBnCL0 bits of the CBnCTL2 register. If a transfer data length of other than 16 bits is specified, set data in the CBnTX or CBnRX register, jus- tifying to the least significant bit, regardless of whether the first transfer bit is the MSB or LSB.
Page 442: Interrupt Request Signals
Chapter 13 3-Wire Serial Interface (CSIB) 13.6 Interrupt Request Signals CSIBn can generate the following two types of interrupt request signals. • Reception complete interrupt request signal (INTCBnR) • Transmission enable interrupt request signal (INTCBnT) Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower.
Page 443: Operation
Chapter 13 3-Wire Serial Interface (CSIB) 13.7 Operation 13.7.1 Single transfer mode (master mode, transmission/reception mode) Figure 13-9 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of CBnCTL0 register = 0), when the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 0, and when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
Page 444: Single Transfer Mode (Master Mode, Reception Mode)
Chapter 13 3-Wire Serial Interface (CSIB) 13.7.2 Single transfer mode (master mode, reception mode) Figure 13-10 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of CBnCTL0 register = 0), when the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 0, and when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
Page 445: Continuous Mode (Master Mode, Transmission/Reception Mode)
Chapter 13 3-Wire Serial Interface (CSIB) 13.7.3 Continuous mode (master mode, transmission/reception mode) Figure 13-11 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of CBnCTL0 register = 0), when continuous transfer mode (CBnTMS bit of CBnCTL0 register = 1), when the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 0, and when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
Page 446: Continuous Mode (Master Mode, Reception Mode)
Chapter 13 3-Wire Serial Interface (CSIB) 13.7.4 Continuous mode (master mode, reception mode) Figure 13-12 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of CBnCTL0 register = 0), when continuous transfer mode (CBnTMS bit of CBnCTL0 register = 1), when the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 1, and when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
Page 447: Continuous Reception Mode (Error)
Chapter 13 3-Wire Serial Interface (CSIB) 13.7.5 Continuous reception mode (error) Figure 13-13 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of CBnCTL0 register = 0), when continuous transfer mode (CBnTMS bit of CBnCTL0 register = 1), when the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 1, and when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
Page 448: Continuous Mode (Slave Mode, Transmission/Reception Mode)
Chapter 13 3-Wire Serial Interface (CSIB) 13.7.6 Continuous mode (slave mode, transmission/reception mode) Figure 13-14 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of CBnCTL0 register = 0), when continuous transfer mode (CBnTMS bit of CBnCTL0 register = 1), when the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 1, and when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
Page 449: Continuous Mode (Slave Mode, Reception Mode)
Chapter 13 3-Wire Serial Interface (CSIB) 13.7.7 Continuous mode (slave mode, reception mode) Figure 13-15 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of CBnCTL0 register = 0), when continuous transfer mode (CBnTMS bit of CBnCTL0 register = 1), when the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 0, and when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
Page 450: Clock Timing
Chapter 13 3-Wire Serial Interface (CSIB) 13.7.8 Clock timing Figure 13-16: Clock Timing (1/2) (a) CBnCKP = 0, CBnDAP = 0 SCKBn SIBn capture SOBn Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF (b) CBnCKP = 1, CBnDAP = 0 SCKBn SIBn capture SOBn Reg-R/W...
Page 451 Chapter 13 3-Wire Serial Interface (CSIB) Figure 13-16: Clock Timing (2/2) (c) CBnCKP = 0, CBnDAP = 1 SCKBn SIBn capture SOBn Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF (d) CBnCKP = 1, CBnDAP = 1 SCKBn SIBn capture SOBn Reg-R/W INTCBnT interrupt INTCBnR...
Page 452: Output Pin Status With Operation Disabled
Chapter 13 3-Wire Serial Interface (CSIB) 13.7.9 Output pin status with operation disabled SCKBn pin The output status of the SCKBn pin is as follows when CSIBn operation is disabled (when the CBnPWR bit of the CBnCTL0 register = 0). CBnCKP SCKBn Pin Output Fixed to high level...
Page 453: Operation Flow
Chapter 13 3-Wire Serial Interface (CSIB) 13.8 Operation Flow Single transmission Figure 13-17: Single Transmission Flow START Initial setting Note CBnCTL0 /CBnCTL1, etc. Write CBnTX register (=> start transfer) INTCBnR = 1? Transfer end? CBnPWR=0 (CBnCTL0 register) Note: Set the CBnSCE bit to 1 at the initial setting. User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com...
Page 454 Chapter 13 3-Wire Serial Interface (CSIB) Single reception (master) Figure 13-18: Single Reception Flow (Master) START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnRX dummy read INTCBnR = 1? Transfer end? CBnSCE = 0 (CBnCTL0) CBnRX read CBnRX read CBnPWR = 0 (CBnCTL0) Note: Set the CBnSCE bit to 1 at the initial setting.
Page 455 Chapter 13 3-Wire Serial Interface (CSIB) Single Transmission/reception Figure 13-19: Single Transmission/Reception Flow (Master) START Initial settings Note 1 CBnCTL0 /CBnCTL1, etc. Note 2 Write CBnTX (=> start transfer) INTCBnR = 1? Transmission only Transmission/reception or reception only CBnRX read Transfer end? CBnPWR = 0, CBnTXE=CBnRXE=0...
Page 456 Chapter 13 3-Wire Serial Interface (CSIB) Single reception (slave) Figure 13-20: Single Reception Flow (Slave) START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnRX dummy read INTCBnR = 1? CBnRX read Transfer end? CBnPWR = 0 (CBnCTL0) Note: Set the CBnSCE bit to 1 at the initial setting. User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com...
Page 457 Chapter 13 3-Wire Serial Interface (CSIB) Continuous transmission Figure 13-21: Continuous Transmission Flow START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnTX write (=> transfer start) INTCBnT = 1? Transfer end? CBnPWR = 0 (CBnCTL0) Note: Set the CBnSCE bit to 1 at the initial setting. Remark: The flow shown below the broken lines is the flow of transmission.
Page 458 Chapter 13 3-Wire Serial Interface (CSIB) Continuous reception (master) Figure 13-22: Continuous Reception Flow (Master) START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnRX dummy read INTCBnR = 1? Last Transmission? CBnSCE = 0 (CBnCTL0) CBnRX read CBnRX read INTCBnR = 1? CBnRX read CBnPWR = 0 (CBnCTL0)
Page 459 Chapter 13 3-Wire Serial Interface (CSIB) Figure 13-23: Continuous Transmission/Reception Flow (Master) START Initial settings Note CBnCTL0 /CBnCTL1, etc. Write CBnTX register (=> start transfer) INTCBnT = 1? Last transmission? Write CBnTX register) INTCBnT = 1? Read CBnRX register) Last transfer? CBnPWR = 0 (CBnCTL0) Note: Set the CBnSCE bit to 1 at the initial setting.
Page 460 Chapter 13 3-Wire Serial Interface (CSIB) Continuous reception (slave) Figure 13-24: Continuous Reception Flow (Slave) START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnRX dummy read INTCBnR = 1? CBnRX read Transfer end? CBnPWR = 0 (CBnCTL0) Note: Set the CBnSCE bit to 1 at the initial setting. Remark: The flow shown below the broken lines is the flow of transmission.
Page 461: Prescaler 3
Chapter 13 3-Wire Serial Interface (CSIB) 13.9 Prescaler 3 Prescaler 3 has the following function. • Generation of count clock for watch timer and CSIB0 (source clock: main oscillation clock) 13.9.1 Control registers of prescaler 3 Prescaler mode register 0 (PRSM0) The PRSM0 register is used to control generation of the count clock for the watch timer and CSIB0.
Page 462: Generation Of Count Clock
Chapter 13 3-Wire Serial Interface (CSIB) Prescaler compare register 0 (PRSCM0) This is an 8-bit compare register. It can be read or written in 8-bit units. Reset input clears this register to 00H. Cautions: 1. Do not rewrite the PRSCM0 register while the watch timer is operating. 2.
Page 463: Chapter 14 Queued Csi (Csi30, Csi31)
Chapter 14 Queued CSI (CSI30, CSI31) 14.1 Features • 3-wire serial synchronous transfers • The following 7 pins are provided to enable a 3-wire serial interface: SO3 (serial data output) SI3 (serial data input) SCK3 (serial clock I/O) CS30 - CS33 (Chip Select) •...
Page 464: Queued Csi Block Diagram
Chapter 14 Queued CSI (CSI30, CSI31) 14.1.1 Queued CSI Block Diagram Figure 14-1: Queued CSI Block Diagram NPB (NEC Peripheral Bus) 16 x 2 Window Register INTC3nO FIFO Full 20 bits x 16 elements Flag Pointer SCK3n SO3n SI3n CS3n0...
Page 465: Queued Csi Control Registers
Chapter 14 Queued CSI (CSI30, CSI31) 14.2 Queued CSI Control Registers Register Map The tables below show the Special Function Registers for the Queued CSI modules CSI30 and CSI31. Table 14-2: CSI30 Access Register name Function Address Reset Value 1-bit 8-bit 16-bit Queued CSI operation mode...
Page 466 Chapter 14 Queued CSI (CSI30, CSI31) Queued CSI Operation Mode Registers (CSIM0, CSIM1) The CSIM registers control the Queued CSI macro's operations. These registers can be read or written in 1-bit and 8-bit units. TRMD, DIR, CSIT, CSWE, CSMD bits can only be written when CTXE = 0 and CRXE = 0. The registers are initialized to 00H at reset.
Page 467 Chapter 14 Queued CSI (CSI30, CSI31) Figure 14-2: Queued CSI Operation Mode Registers (CSIM0, CSIM1) Format (2/2) Serial data direction selection Data is sent/received with MSB first Data is sent/received with LSB first Caution: Write is permitted only when CTXE = 0 and CRXE = 0. See section 14.3.2 ”Serial Data Direction Select Function”...
Page 468 Chapter 14 Queued CSI (CSI30, CSI31) Queued CSI Clock Selection Registers (CSIC0, CSIC1) The CSIC register is an 8-bit register that is used to control the serial transfer operations. This register can be read or written in 1-bit and in 8-bit units. Caution: This register can be written only while CSIM register's CTXE = 0 and CRXE = 0.
Page 469 Chapter 14 Queued CSI (CSI30, CSI31) Figure 14-3: Queued CSI Clock Selection Registers (CSIC0, CSIC1) Format (2/2) Prescaler output CKS2 CKS1 CKS0 Mode (PRSOUT) Master Mode QCSI Master Mode QCSI Master Mode QCSI Master Mode QCSI Master Mode QCSI Master Mode QCSI Master Mode QCSI...
Page 470 Chapter 14 Queued CSI (CSI30, CSI31) The baudrate for the transmission is calculated with the following formula: Transmission Baud Rate = f/(N*2(K+1)) where: f: f frequency, QCSI N = 1 - 7, K = 0 - 6. Figure 14-4: Queued CSI Baud Rate Block Diagram SCK3 (input) Transfer clock PRSOUT...
Page 471 Chapter 14 Queued CSI (CSI30, CSI31) Receive Data Buffer Registers (SIRB0, SIRB1) The SIRB register is a 16-bit register or separated as upper 8 bits (SIRBH) and lower 8 bits (SIRBL), that is used to store receive data. This register can be read in 8-bit or 16-bit units and is initialized to 0000H by reset.
Page 472 Chapter 14 Queued CSI (CSI30, CSI31) Transmission Data Buffer registers (SFDB0, SFDB1) The SFDB register is a 16-bit buffer register, or separated as upper 8 bits (SFDBH) and lower 8 bits (SFDBL), that stores transmission data. The SFDB register is read/write-enabled and is accessible in 8-bit or 16-bit units.
Page 473 Chapter 14 Queued CSI (CSI30, CSI31) Figure 14-8: FIFO Buffer Status Registers (SFA0, SFA1) Format (2/2) SFFUL FIFO buffer full status flag FIFO buffer is not full FIFO buffer is full Remark: Read only SFEMP FIFO buffer empty status flag FIFO buffer is not empty FIFO buffer is empty Remark:...
Page 474 Chapter 14 Queued CSI (CSI30, CSI31) Queued CSI Data Length Selection Registers (CSIL0, CSIL1) The CSIL register is an 8-bit register that specifies the active voltage level of the Chip Select pins and the Queued CSI data length. This register can be read or written in 1-bit and 8-bit units. This register can be overwritten only while CTXE = 0 and CRXE = 0 (CSIM register).
Page 475 Chapter 14 Queued CSI (CSI30, CSI31) Queued CSI Transfer Number Selection Registers (SFN0, SFN1) The SFN register is an 8-bit register that specifies the number of data elements to be transferred in FIFO buffer transfer mode. It can be read or written in 1-bit and 8-bit units. Initial value is 00H by reset.
Page 476: Explanation Of Queued Csi Functions
Chapter 14 Queued CSI (CSI30, CSI31) 14.3 Explanation of Queued CSI Functions 14.3.1 Transmit Buffer Chip select data and transmission data can be stored to the transmit FIFO buffer continuously by writing to the SFCS register and SFDB register. The Writing FIFO pointer is automatically incremented when data is written to SFDB.
Page 477: Serial Data Direction Select Function
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.2 Serial Data Direction Select Function The serial data direction is selectable using the DIR bit in the CSIM register. The examples below show the communication for data length of 8 bit (CCL[3:0] = [1,0,0,0]): Figure 14-12: Serial Data Direction Select Function (a) MSB first (DIR = 0) SCK3...
Page 478: Data Length Select Function
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.3 Data Length Select Function Transmission data length is selectable from 8 bits to 16 bits using the CCL[3:0] bits in CSIL register. The examples below show the communication with MSB first (DIR = 1): Figure 14-13: Data Length Select Function CCL[3:0] = [0,0,0,0] (data length = 16): SCK3...
Page 479: Slave Mode
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.4 Slave Mode When the CKS[2:0] bits in CSIC are set to [1,1,1], the Queued CSI operates in slave mode. In slave mode, the SCK3 serial clock pin becomes input and another device is the CSI communication master. The baud rate generator “BRG”...
Page 480: Transmission Clock Select Function
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.6 Transmission Clock Select Function In Master Mode, the transfer baud rate is selectable using CKS[2:0] bits and MDL[2:0] bits in CSIC reg- ister. The baud rate generator “BRG” counts up at each rising edge of f QCSI The example below illustrates the baud rate generation for MDL[2:0] = [0,1,0].
Page 481: Description Of The Single Buffer Transfer Mode
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.7 Description of the Single Buffer Transfer Mode Figure 14-17: Single Buffer Transfer Mode Data Handling 16 15 Data 3, 2, 1, 0 15, 14, 13, ..2, 1, 0 Writing FIFO CS data 5 pointer CS data 4 Transmission data 4...
Page 482 Chapter 14 Queued CSI (CSI30, CSI31) When a transfer finishes and the FIFO buffer is empty (Writing FIFO pointer = SIO Loading FIFO pointer), CSOT is cleared “0”. SFP[3:0] always show the current value of: (Writing FIFO pointer) - (SIO Loading FIFO pointer). It is recommended to check that SFFUL = 0 just before data is written to the SFDB register.
Page 483: Description Of The Fifo Buffer Transfer Mode
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.8 Description of the FIFO Buffer Transfer Mode When the TRMD bit in the CSIM register is set “1”, the Queued CSI operates in FIFO buffer transfer mode. Figure 14-19: FIFO Buffer Transfer Mode Data Handling Data 3, 2, 1, 0 15, 14, 13, ..
Page 484 Chapter 14 Queued CSI (CSI30, CSI31) When the transmission/reception counter reaches the value set by SFN[3:0], then CSOT is cleared “0” and the transmission/reception end interrupt signal INTC3nI is generated. After the interrupt occurred, the received data can be read from SIRB. The Read FIFO pointer is auto- matically incremented by the SIRB read operation.
Page 485: Description Of The Operation Modes
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.9 Description of the Operation Modes Transmit Only Mode Setting the CSIM register's CTXE =1 and CRXE = 0 places the Queued CSI in transmit only mode. A transmission starts when transmit data is written in the SFDB register. The current condition of the SIRB buffer and SIO register no effect.
Page 486: Additional Timing And Delay Selections
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.10 Additional Timing and Delay Selections Delay Selection of Receive Termination Interrupt Signal (INTC3nI) In master mode, the CSIT bit of the CSIM register can be used to delay the generation of the receive termination interrupt signal (INTC3nI) by a half serial clock cycle (SCK3). The CSIT bit takes effect only in the master mode and is ignored in slave mode.
Page 487 Chapter 14 Queued CSI (CSI30, CSI31) Selection of Transmit Wait Enable/Disable In master mode, the CSIM register's CSWE bit setting can be used to delay the start of transmis- sion by one SCK3 clock cycle. The CSWE bit takes effect only in the master mode and is ignored in slave mode.
Page 488 Chapter 14 Queued CSI (CSI30, CSI31) Figure 14-23: Selection of Chip-Select Mode CSIT=0, CSWE=0, CSMD=0 or 1: SCK3 INTC3nI Inactive level is not output CS3n[3:0] CSIT=0, CSWE=1, CSMD=1: wait SCK3 INTC3nI Inactive level comes out CS3n[3:0] CSIT=1, CSWE=1, CSMD=1: delay wait SCK3 INTC3nI...
Page 489: Default Pin Levels
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.11 Default Pin Levels SCK3 Pin's Default Level SCK3 pin's default level with the CSIM register settings POWER = 0 or CTXE / CRXE = 0 CKS2, CKS1, CKS0 SCK3 default level ← Initialization after reset 1, 1, 1 (slave mode) Other than 1, 1, 1 (master mode) 1, 1, 1 (slave mode)
Page 490: Transmit Buffer Overflow Interrupt Signal (Intc3No)
Chapter 14 Queued CSI (CSI30, CSI31) 14.3.12 Transmit Buffer Overflow Interrupt Signal (INTC3nO) When the transmit FIFO buffer contains 16 elements, writing a 17th chip-select data (SFCS write) or transfer data (SFDB write) results in the generation of the overflow interrupt INTC3nO. For the 17th item, both chip-select and transfer data values are discarded.
Page 491: Operating Procedure
Chapter 14 Queued CSI (CSI30, CSI31) 14.4 Operating Procedure Single Buffer Transfer Mode (Master Mode, Transmit Only Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT=0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 0, DAP = 0, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-25: Single Buffer Transfer Mode (Master, Transmit Only) Timing CTXE...
Page 492 Chapter 14 Queued CSI (CSI30, CSI31) Single Buffer Transfer Mode (Master Mode, Receive Only Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 0, DAP = 1, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-26: Single Buffer Transfer Mode (Master, Receive Only) Timing CRXE...
Page 493 Chapter 14 Queued CSI (CSI30, CSI31) Single Buffer Transfer Mode (Master Mode, Transmit/Receive Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 1, DAP = 0, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-27: Single Buffer Transfer Mode (Master, Transmit/Receive) Timing CTXE, CRXE...
Page 494 Chapter 14 Queued CSI (CSI30, CSI31) Single Buffer Transfer Mode (Slave Mode, Transmit Only Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 1, DAP = 1, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-28: Single Buffer Transfer Mode (Slave, Transmit Only) Timing CTXE...
Page 495 Chapter 14 Queued CSI (CSI30, CSI31) Single Buffer Transfer Mode (Slave Mode, Receive Only Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 0, DAP = 0, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-29: Single Buffer Transfer Mode (Slave, Receive Only) Timing CRXE...
Page 496 Chapter 14 Queued CSI (CSI30, CSI31) Single Buffer Transfer Mode (Slave Mode, Transmit/Receive Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 0, DAP = 1, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-30: Single Buffer Transfer Mode (Slave, Transmit/Receive) Timing CTXE, CRXE...
Page 497 Chapter 14 Queued CSI (CSI30, CSI31) FIFO Buffer Transfer Mode (Master Mode, Transmit Only Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 0, DAP = 0, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-31: FIFO Buffer Transfer Mode (Master, Transmit Only) Timing CTXE...
Page 498 Chapter 14 Queued CSI (CSI30, CSI31) FIFO Buffer Transfer Mode (Master Mode, Receive Only Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 0, DAP = 1, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-32: FIFO Buffer Transfer Mode (Master, Receive Only) Timing CRXE...
Page 499 Chapter 14 Queued CSI (CSI30, CSI31) FIFO Buffer Transfer Mode (Master Mode, Transmit/Receive Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 1, DAP = 0, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-33: FIFO Buffer Transfer Mode (Master, Transmit/Receive) Timing CTXE, CRXE...
Page 500 Chapter 14 Queued CSI (CSI30, CSI31) (10) FIFO Buffer Transfer Mode (Slave Mode, Transmit Only Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 1, DAP = 1, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-34: FIFO Buffer Transfer Mode (Slave, Transmit Only) Timing CTXE...
Page 501 Chapter 14 Queued CSI (CSI30, CSI31) (11) FIFO Buffer Transfer Mode (Slave Mode, Receive Only Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 0, DAP = 0, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-35: FIFO Buffer Transfer Mode (Slave, Receive Only) Timing CRXE...
Page 502 Chapter 14 Queued CSI (CSI30, CSI31) (12) FIFO Buffer Transfer Mode (Slave Mode, Transmit/Receive Mode) MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS inactive disabled (CSMD = 0), CKP = 0, DAP = 1, transmission data length of 8 bits (CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”: Figure 14-36: FIFO Buffer Transfer Mode (Slave, Transmit/Receive) Timing CTXE, CRXE...
Page 503: Chapter 15 Dma Functions (Dma Controller)
Chapter 15 DMA Functions (DMA Controller) V850E/RS1 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfers. It supports transfers of data between internal or external memory and peripheral I/O, between internal and external memory, or between peripheral I/Os. DMA requests can be issued by the on-chip peripheral I/O (like serial interface, real-time pulse unit, or A/D converter), by interrupts from external input pins, or they can be triggered by software.
Page 504: Configuration
Chapter 15 DMA Functions (DMA Controller) 15.2 Configuration Figure 15-1: DMA Block Diagram Transmit control block Address control block Data control block Control registers DMA control register (DMC) DMA source address register (DMSAn) DMA destination addressing register (DMDAn) DMA addressing control register Count control block (DMADCn) DMA transmit count register...
Page 505: Control Registers
Chapter 15 DMA Functions (DMA Controller) 15.3 Control Registers DMA control register (DMC) The DMC register controls the operation and the clock supply of the DMA controller. It can be read or written in 8-bit or 1-bit units. Initial value is 00H by reset. Figure 15-2: DMA Control Register (DMC) Format Symbol Address...
Page 506 Chapter 15 DMA Functions (DMA Controller) Figure 15-3: IDMEN Bit and NMI Handling IDMEN=0: DMMRQ processing NMI detected, but processing delayed until DMA is finished IDMEN=1: DMMRQ processing STPDIS NMI interrupts DMA cycle immediately STPCLR Transfer Interruption Clear Trigger Bit No change Release all interrupted and stopped DMA transfers and resume operation.
Page 507 Chapter 15 DMA Functions (DMA Controller) DMA channel status flag register (DMSF) The DMSF register shows the DMA transfer status of each DMA channel. It is a direct mirror of all ACF bits (DMCHCn register). It can be read in 16-bit units only. The register is initialized by POWER = 0.
Page 508 Chapter 15 DMA Functions (DMA Controller) Figure 15-5: DMA Source Address Register (DMSAn) Format (2/2) Selected chip and selection area CS0 is selected. CS1 is selected. Setting prohibited Cautions: 1. When the DMA transfer object is in the external memory area, set the valid chip select signal for SC[2:0].
Page 509 Chapter 15 DMA Functions (DMA Controller) DMA destination address register (DMDAn) The DMDAn register is used to set the DMA destination address. When the TDIR bit (DMADCn register) is 0, it holds the address the data is transferred to (destination), for TDIR=1 the register holds the address data is transferred from (source).
Page 510 Chapter 15 DMA Functions (DMA Controller) Figure 15-6: DMA Destination Address Register (DMDAn) Format (2/2) DMA transfer destination address (address signals A25 - A0). DA25 - DA0 If address increment is selected for the DMA transfer, the address will be updated after each transfer to the next transfer address.
Page 511 Chapter 15 DMA Functions (DMA Controller) DMA addressing control register (DMADCn) The DMADCn register control the address handling for each DMA channel. It can be read or writ- ten in 8-bit or 16-bit units. Initial value is F000H by reset. Caution: Write to DMADCn is permitted only when EN = 0 (DMCHCn register).
Page 512 Chapter 15 DMA Functions (DMA Controller) Figure 15-8: DMA Addressing Control Register (DMADCn) Format (2/2) Destination Address Count Mode (DA[25:0] bits) Destination address is incremented after each transfer. Destination address is fixed Selected DMA Transfer Size Byte (8-bit) Half word (16-bit) Word (32-bit) Setting prohibited Remark:...
Page 513 DMA controller. For V850E/RS1, there is no sharing of interrupts needed, as each of the DMA channels has its own interrupt assigned on interrupt controller side. Therefore it is highly recommended NOT to use the TCS=0 setting.
Page 514 Chapter 15 DMA Functions (DMA Controller) Figure 15-10: DMA Channel Control Register (DMCHCn) Format (2/4) DMA Acknowledge Flag No DMA transfer in progress. Indicate the DMA transfer status. When ACF is set (1), the state is different depending on the transfer mode. Single or Fixed Channel transfer mode: DMA transfer has been executed at least one time, but the total number of transfers has not yet been reached.
Page 515 Chapter 15 DMA Functions (DMA Controller) Figure 15-10: DMA Channel Control Register (DMCHCn) Format (3/4) (b) ACF bit status in channel-fixed single transfer mode DMBC0 = 02H (3-times transfer) DMBC3 = 03H (4-times transfer) Bus status DMA3 DMA3 DMA3 DMA3 DMA0 DMA0 DMA0...
Page 516 Chapter 15 DMA Functions (DMA Controller) Figure 15-10: DMA Channel Control Register (DMCHCn) Format (4/4) FCLR DMA Request Clear Trigger No change Clear any pending DMA transfer request. Caution: Write to FCLR = 1 is permitted only when EN = 0 (DMCHCn register). Remarks: 1.
Page 517 Chapter 15 DMA Functions (DMA Controller) DMA trigger factor register (DTFRn) The DTFRn register selects the DMA transfer start trigger through interrupt. The interrupt source selected in this register serves as trigger to start the DMA transfer. The register can be read or written in 8-bit or 1-bit units. However, only bit 7 (DFn) can be read/ written in 1-bit units.
Page 518: Table 15-1: Interrupt Source For Dma Trigger Factor Register (Dtfrn) (1/2
Chapter 15 DMA Functions (DMA Controller) Cautions: 3. An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP, or sub-IDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1). 4. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an interrupt occurs from the selected on-chip peripheral I/O, regardless of whether the DMA transfer is enabled or disabled.
Page 519 Chapter 15 DMA Functions (DMA Controller) Table 15-1: Interrupt Source for DMA Trigger Factor Register (DTFRn) (2/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source INTUA1R INTUA1T INTAD INTC0ERR INTC0WUP INTC0REC INTC0TRX INTC30I INTC30O INTC31I INTC31O Setting prohibited Setting prohibited INTTQ1OV INTTQ1CC0 INTTQ1CC1...
Page 520: Dma Transfer Rules
Chapter 15 DMA Functions (DMA Controller) 15.4 DMA Transfer Rules 15.4.1 Transfer targets Table 15-2 shows the available source and destination selections for the DMA transfer: Table 15-2: Transfer Targets Destination On-chip Peripheral I/O Internal RAM Internal ROM External memory √...
Page 521: Dma Transfer End
Figure 15-12 illustrates the timing of INTDMAn for the two TCS settings. As mentioned before, the mirror function is not required for V850E/RS1, therefore it is highly recommended NOT to use a setting of TCS=0. Figure 15-12: TCS Bit and INTDMAn Generation...
Page 522: Transfer Modes
Chapter 15 DMA Functions (DMA Controller) 15.5 Transfer Modes In the following examples it is assumed that TCS is set as “1” for all DMA channels. 15.5.1 Single transfer mode In Single transfer mode, the DMA releases the bus after each transfer. If there is a subsequent DMA transfer request, the transfer is performed again when the bus becomes available again.
Page 523: Fixed Channel Transfer Mode
Chapter 15 DMA Functions (DMA Controller) 15.5.2 Fixed channel transfer mode In “Fixed Channel” transfer mode, the DMA releases the bus after each transfer, but continues to repeat the DMA transfer until the transfer counter is cleared to 0 without requiring a new DMA transfer request. When the DMA has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request does not take precedence.
Page 524: Block Transfer Mode
Chapter 15 DMA Functions (DMA Controller) 15.5.3 Block transfer mode In Block transfer mode, once transfer starts, DMA continues the transfer operation without releasing the bus until the set number of transfers is done and the TC signal is set. No other DMA request is acknowl- edged during that Block transfer.
Page 525: Chapter 16 Fcan Controller
Chapter 16 FCAN Controller 16.1 Overview This product features an on-chip 2-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The number of channels varies depending on the product as shown below. 16.1.1 Features •...
Page 526: Overview Of Functions
Chapter 16 FCAN Controller 16.1.2 Overview of Functions Table 16-1 presents an overview of the CAN controller functions. Table 16-1: Overview of Functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Baud rate Maximum 1 Mbps (CAN clock input Š 8 MHz) Data storage Storing messages in the CAN RAM •...
Page 527: Configuration
16.1.3 Configuration The CAN controller is composed of the following four blocks. NPB interface This functional block provides an NPB (NEC Peripheral I/O Bus) interface and means of transmit- ting and receiving signals between the CAN module and the host CPU.
Page 528: Can Protocol
Chapter 16 FCAN Controller 16.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time commu- nication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer.
Page 529: Frame Types
Chapter 16 FCAN Controller 16.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 16-2: Frame Types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame...
Page 530 Chapter 16 FCAN Controller Remote frame A remote frame is composed of six fields. Figure 16-4: Remote Frame Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks: 1.
Page 531: Table 16-3: Rtr Frame Settings
Chapter 16 FCAN Controller <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 16-6: Arbitration Field (in Standard Format Mode) Arbitration field (Control field) Identifier (r1) ID28 · · · · · · · · · · · · · · · · · · · · ID18 (11 bits) (1 bit) (1 bit)
Page 532: Table 16-4: Frame Format Setting (Ide Bit) And Number Of Identifier (Id) Bits
Chapter 16 FCAN Controller Table 16-4: Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits Frame Format SRR Bit IDE Bit Number of Bits Standard format mode None 0 (D) 11 bits Extended format mode 1 (R) 1 (R) 29 bits <3>...
Page 533 Chapter 16 FCAN Controller <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 16-9: Data Field (Control field) Data field (CRC field) Data 0 Data 7 (8 bits)
Page 534 Chapter 16 FCAN Controller <6> ACK field The ACK field is used to acknowledge normal reception. Figure 16-11: ACK Field (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Remark: D: Dominant = 0 R: Recessive = 1 •...
Page 535 Chapter 16 FCAN Controller <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. • The bus state differs depending on the error status. (a) Error active node The interframe space consists of a 3-bit intermission field and a bus idle field.
Page 536: Table 16-6: Operation In Error Status
Chapter 16 FCAN Controller (b) Error passive node The interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. Figure 16-14: Interframe Space (Error Passive Node) (Frame) Interframe space (Frame) Intermission Suspend transmission Bus idle (0 to ∞...
Page 537: Error Frame
Chapter 16 FCAN Controller 16.2.4 Error frame An error frame is output by a node that has detected an error. Figure 16-15: Error Frame Error frame (<4>) <1> <2> <3> (<5>) 6 bits 0 to 6 bits 8 bits Interframe space or overload frame Error delimiter Error flag 2 Error flag 1...
Page 538: Overload Frame
Chapter 16 FCAN Controller 16.2.5 Overload frame An overload frame is transmitted under the following conditions. • When the receiving node has not completed the reception operation • If a dominant level is detected at the first two bits during intermission •...
Page 539: Functions
Chapter 16 FCAN Controller 16.3 Functions 16.3.1 Determining bus priority When a node starts transmission: During bus idle, the node that output data first transmits the data. When more than one node starts transmission: The node that consecutively outputs the dominant level for the longest from the first bit of the arbi- tration field has the bus priority (if a dominant level and a recessive level are simultaneously trans- mitted, the dominant level is taken as the bus value).
Page 540: Multi Masters
Chapter 16 FCAN Controller 16.3.3 Multi masters As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. 16.3.4 Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes.
Page 541: Table 16-12: Output Timing Of Error Frame
Chapter 16 FCAN Controller Output timing of error frame Table 16-12: Output Timing of Error Frame Type Output Timing Bit error, stuff error, Error frame output is started at the timing of the bit following the detected error. form error, ACK error CEC error Error frame output is started at the timing of the bit following the ACK delimiter.
Page 542: Table 16-13: Types Of Error States
Chapter 16 FCAN Controller Table 16-13: Types of Error States Value of Error Indication of CnINFO Type Operation Operation Specific to Error State Counter Register Transmission 0 to 95 TECS1, TECS0 = 00 Reception 0 to 95 RECS1, RECS0 = 00 Error •...
Page 543: Table 16-14: Error Counter
Chapter 16 FCAN Controller (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful trans- mission and reception. The error counter is updated during the first bit of the error delimiter. Table 16-14: Error Counter Transmission Reception State...
Page 544 Chapter 16 FCAN Controller Recovery from bus-off state When the CAN module is in the bus-off state, the transmission pins (CTXDn) cut off from the CAN bus always output the recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence. <1>...
Page 545 Chapter 16 FCAN Controller Figure 16-17: Recovery from Bus-off State Through Normal Recovery Sequence TEC > FFH »bus-off« »bus-off-recovery-sequence« »error-active« »error-passive« BOFF bit in CnINFO register <1> <2> OPMODE[2:0] in CnCTRL ≠ 00H ≠ 00H register (written by user) <3> OPMODE[2:0] in CnCTRL ≠...
Page 546 Chapter 16 FCAN Controller (c) Initializing CAN module error counter register (CnERC) in initialization mode If it is necessary to initialize the CAN module error counter register (CnERC) and CAN module information register (CnINFO) for debugging or evaluating a program, they can be initialized to the default value by setting the CCERC bit of the CnCTRL register in the initialization mode.
Page 547: Baud Rate Control Function
Chapter 16 FCAN Controller 16.3.7 Baud rate control function Prescaler The CAN controller has a prescaler that divides the clock (f ) supplied to CAN. This prescaler generates a CAN protocol layer base clock (f ) that is the CAN module system clock (f CANMOD divided by 1 to 256 (refer to 16.6 (12)”CAN module bit rate prescaler register (CnBRP)”...
Page 548 Chapter 16 FCAN Controller Reference: The CAN protocol specification defines the segments constituting the data bit time as shown in Figure 16-19. Figure 16-19: Reference: Configuration of Data Bit Time Defined by CAN Specification Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point (SPT)
Page 549 Chapter 16 FCAN Controller Synchronizing data bit • The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. • The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
Page 550 Chapter 16 FCAN Controller (b) Resynchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). • The phase error of the edge is given by the relative position of the detected edge and sync segment.
Page 551: Connection With Target System
Chapter 16 FCAN Controller 16.4 Connection with Target System The CAN module has to be connected to the CAN bus using an external transceiver. Figure 16-22: Connection to CAN Bus CTxDn CANL CAN module Transceiver CRxDn CANH Remark: n = 0, 1 User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com...
Page 552: Internal Registers Of Can Controller
Chapter 16 FCAN Controller 16.5 Internal Registers of CAN controller 16.5.1 CAN controller configuration Table 16-15: List of CAN Controller Registers Item Register Name CAN global control register (CnGMCTRL) CAN global clock selection register (CnGMCS) CAN global registers CAN global automatic block transmission control register (CnGMABT) CAN global automatic block transmission delay setting register (CnGMABTD) CAN module mask 1 register (CnMASK1L, CnMASK1H) CAN module mask 2 register (CnMASK2L, CnMASK2H)
Page 553: Register Access Type
Chapter 16 FCAN Controller 16.5.2 Register access type The peripheral I/O register for the CAN controller is assigned to 03FEC000H to 03FEEFFFH. For details, refer to 3.5.1 ”Programmable peripheral I/O control register (BPC)” on page 92. Table 16-16: Register Access Type (1/31) Bit Manipulation Units Address...
Page 554 Chapter 16 FCAN Controller Table 16-16: Register Access Type (2/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC104H CAN0 message data byte 45 register 00 C0MDATA4500 R/W Undefined √ 03FEC104H CAN0 message data byte 4 register 00 C0MDATA400 Undefined √...
Page 555 Chapter 16 FCAN Controller Table 16-16: Register Access Type (3/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC146H CAN0 message data byte 67 register 02 C0MDATA6702 R/W undefined √ 03FEC146H CAN0 message data byte 6 register 02 C0MDATA602 undefined √...
Page 556 Chapter 16 FCAN Controller Table 16-16: Register Access Type (4/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC189H CAN0 message configuration register 04 C0MCONF04 undefined √ 03FEC18AH C0MIDL04 undefined CAN0 message ID register 04 √...
Page 557 Chapter 16 FCAN Controller Table 16-16: Register Access Type (5/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC1E0H CAN0 message data byte 01 register 07 C0MDATA0107 R/W undefined √ 03FEC1E0H CAN0 message data byte 0 register 07 C0MDATA007 undefined √...
Page 558 Chapter 16 FCAN Controller Table 16-16: Register Access Type (6/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC222H CAN0 message data byte 23 register 09 C0MDATA2309 R/W undefined √ 03FEC222H CAN0 message data byte 2 register 09 C0MDATA209 undefined √...
Page 559 Chapter 16 FCAN Controller Table 16-16: Register Access Type (7/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC264H CAN0 message data byte 45 register 11 C0MDATA4511 R/W undefined √ 03FEC264H CAN0 message data byte 4 register 11 C0MDATA411 undefined √...
Page 560 Chapter 16 FCAN Controller Table 16-16: Register Access Type (8/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC2A6H CAN0 message data byte 67 register 13 C0MDATA6713 R/W undefined √ 03FEC2A6H CAN0 message data byte 6 register 13 C0MDATA613 undefined √...
Page 561 Chapter 16 FCAN Controller Table 16-16: Register Access Type (9/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC2E9H CAN0 message configuration register 15 C0MCONF15 undefined √ 03FEC2EAH C0MIDL15 undefined CAN0 message ID register 15 √...
Page 562 Chapter 16 FCAN Controller Table 16-16: Register Access Type (10/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC340H CAN0 message data byte 01 register 18 C0MDATA0118 R/W undefined √ 03FEC340H CAN0 message data byte 0 register 18 C0MDATA018 undefined √...
Page 563 Chapter 16 FCAN Controller Table 16-16: Register Access Type (11/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC382H CAN0 message data byte 23 register 20 C0MDATA2320 R/W undefined √ 03FEC382H CAN0 message data byte 2 register 20 C0MDATA220 undefined √...
Page 564 Chapter 16 FCAN Controller Table 16-16: Register Access Type (12/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC3C4H CAN0 message data byte 45 register 22 C0MDATA4522 R/W undefined √ 03FEC3C4H CAN0 message data byte 4 register 22 C0MDATA422 undefined √...
Page 565 Chapter 16 FCAN Controller Table 16-16: Register Access Type (13/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC406H CAN0 message data byte 67 register 24 C0MDATA6724 R/W undefined √ 03FEC406H CAN0 message data byte 6 register 24 C0MDATA624 undefined √...
Page 566 Chapter 16 FCAN Controller Table 16-16: Register Access Type (14/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC448H CAN0 message data length code register 26 C0MDLC26 0000xxxxB √ 03FEC449H CAN0 message configuration register 26 C0MCONF26 undefined √...
Page 567 Chapter 16 FCAN Controller Table 16-16: Register Access Type (15/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit 00x00000 √ 03FEC48EH CAN0 message control register 28 C0MCTRL28 000xx000B √ 03FEC4A0H CAN0 message data byte 01 register 29 C0MDATA0129 R/W undefined √...
Page 568 Chapter 16 FCAN Controller Table 16-16: Register Access Type (16/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC4E2H CAN0 message data byte 23 register 31 C0MDATA2331 R/W undefined √ 03FEC4E2H CAN0 message data byte 2 register 31 C0MDATA231 undefined √...
Page 569 Chapter 16 FCAN Controller Table 16-16: Register Access Type (17/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit − − √ 03FEC666H CAN1 module time stamp register C1TS 0000H √ 03FEC700H CAN1 message data byte 01 register 00 C1MDATA0100 R/W undefined √...
Page 570 Chapter 16 FCAN Controller Table 16-16: Register Access Type (18/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC742H CAN1 message data byte 23 register 02 C1MDATA2302 R/W undefined √ 03FEC742H CAN1 message data byte 2 register 02 C1MDATA202 undefined √...
Page 571 Chapter 16 FCAN Controller Table 16-16: Register Access Type (19/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC784H CAN1 message data byte 45 register 04 C1MDATA4504 R/W undefined √ 03FEC784H CAN1 message data byte 4 register 04 C1MDATA404 undefined √...
Page 572 Chapter 16 FCAN Controller Table 16-16: Register Access Type (20/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC7C6H CAN1 message data byte 67 register 06 C1MDATA6706 R/W undefined √ 03FEC7C6H CAN1 message data byte 6 register 06 C1MDATA606 undefined √...
Page 573 Chapter 16 FCAN Controller Table 16-16: Register Access Type (21/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC809H CAN1 message configuration register 08 C1MCONF08 undefined √ 03FEC80AH C1MIDL08 undefined CAN1 message ID register 08 √...
Page 574 Chapter 16 FCAN Controller Table 16-16: Register Access Type (22/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC860H CAN1 message data byte 01 register 11 C1MDATA0111 R/W undefined √ 03FEC860H CAN1 message data byte 0 register 11 C1MDATA011 undefined √...
Page 575 Chapter 16 FCAN Controller Table 16-16: Register Access Type (23/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC8A2H CAN1 message data byte 23 register 13 C1MDATA2313 R/W undefined √ 03FEC8A2H CAN1 message data byte 2 register 13 C1MDATA213 undefined √...
Page 576 Chapter 16 FCAN Controller Table 16-16: Register Access Type (24/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC8E4H CAN1 message data byte 45 register 15 C1MDATA4515 R/W undefined √ 03FEC8E4H CAN1 message data byte 4 register 15 C1MDATA415 undefined √...
Page 577 Chapter 16 FCAN Controller Table 16-16: Register Access Type (25/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC926H CAN1 message data byte 67 register 17 C1MDATA6717 R/W undefined √ 03FEC926H CAN1 message data byte 6 register 17 C1MDATA617 undefined √...
Page 578 Chapter 16 FCAN Controller Table 16-16: Register Access Type (26/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC969H CAN1 message configuration register 19 C1MCONF19 undefined √ 03FEC96AH C1MIDL19 undefined CAN1 message ID register 19 √...
Page 579 Chapter 16 FCAN Controller Table 16-16: Register Access Type (27/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FEC9C0H CAN1 message data byte 01 register 22 C1MDATA0122 R/W undefined √ 03FEC9C0H CAN1 message data byte 0 register 22 C1MDATA022 undefined √...
Page 580 Chapter 16 FCAN Controller Table 16-16: Register Access Type (28/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FECA02H CAN1 message data byte 23 register 24 C1MDATA2324 R/W undefined √ 03FECA02H CAN1 message data byte 2 register 24 C1MDATA224 undefined √...
Page 581 Chapter 16 FCAN Controller Table 16-16: Register Access Type (29/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FECA44H CAN1 message data byte 45 register 26 C1MDATA4526 R/W undefined √ 03FECA44H CAN1 message data byte 4 register 26 C1MDATA426 undefined √...
Page 582 Chapter 16 FCAN Controller Table 16-16: Register Access Type (30/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FECA86H CAN1 message data byte 67 register 28 C1MDATA6728 R/W undefined √ 03FECA86H CAN1 message data byte 6 register 28 C1MDATA628 undefined √...
Page 583 Chapter 16 FCAN Controller Table 16-16: Register Access Type (31/31) Bit Manipulation Units Address Register Name Symbol After Reset 1-bit 8-bit 16-bit √ 03FECAC9H CAN1 message configuration register 30 C1MCONF30 undefined √ 03FECACAH C1MIDL30 undefined CAN1 message ID register 30 √...
Page 584: Table 16-17: Can Module Register Bit Configuration
Chapter 16 FCAN Controller Table 16-17: CAN Module Register Bit Configuration (1/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 03FExx40H CM1ID[7:0] CnMASK1L 03FExx41H CM1ID[15:8] 03FExx42H CM1ID[23:16] CnMASK1H 03FExx43H CM1ID[28:24] 03FExx44H CM2ID[7:0] CnMASK2L...
Page 585 Chapter 16 FCAN Controller Table 16-17: CAN Module Register Bit Configuration (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 03FExx5CH TSEG1[3:0] CnBTR 03FExx5DH SJW[1:0] TSEG2[2:0] 03FExx5EH CnLIPT LIPT[7:0] Clear 03FExx60H CnRGPT ROVF...
Page 586: Register Bit Configuration
Chapter 16 FCAN Controller 16.5.3 Register bit configuration Table 16-18: CAN Global Register Bit Configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 Clear 03FExx00H CnGMCTRL (W) 03FExx01H EFSD 03FExx00H EFSD CnGMCTRL (R) 03FExx01H...
Page 587: Table 16-19: Message Buffer Register Bit Configuration
Chapter 16 FCAN Controller Table 16-19: Message Buffer Register Bit Configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 03FExxx0H Message data (byte 0) CnMDATA01m 03FExxx1H Message data (byte 1) 03FExxx0H CnMDATA0m Message data (byte 0)
Page 588: Control Registers
Chapter 16 FCAN Controller 16.6 Control Registers CAN global control register (CnGMCTRL) The CnGMCTRL register is used to control the operation of the CAN module. Figure 16-23: CAN Global Control Register (CnGMCTRL) Format (1/2) (a) Read Address R/W After reset CnGMCTRL MBON 0000H see Table...
Page 589 Chapter 16 FCAN Controller Figure 16-23: CAN Global Control Register (CnGMCTRL) Format (2/2) EFSD Bit enabling forced shut down Forced shut down by GOM = 0 disabled. Forced shut down by GOM = 0 enabled. Caution: To request forced shut down, the GOM bit must be cleared to 0 immediately after the EFSD bit has been set to 1.
Page 590 Chapter 16 FCAN Controller CAN global clock selection register (CnGMCS) The CnGMCS register is used to select the CAN module system clock. Figure 16-24: CAN Global Clock Selection Register (CnGMCS) Format Address R/W After reset see Table CnGMCS CCP3 CCP2 CCP1 CCP0 16-4...
Page 591 Chapter 16 FCAN Controller CAN global automatic block transmission control register (CnGMABT) The CnGMABT register is used to control the automatic block transmission (ABT) operation. Figure 16-25: CAN Global Automatic Block Transmission Control Register (CnGMABT) Format (1/2) (a) Read Address R/W After reset CnGMABT 0000H see Table...
Page 592 Chapter 16 FCAN Controller Figure 16-25: CAN Global Automatic Block Transmission Control Register (CnGMABT) Format (2/2) (b) Write Set ABTCLR Automatic block transmission engine clear request bit The automatic block transmission engine is in idle state or under operation. Request to clear the automatic block transmission engine. After the automatic block trans- mission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the ABTTRG bit to 1.
Page 593 Chapter 16 FCAN Controller CAN global automatic block transmission delay register (CnGMABTD) The CnGMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT. Figure 16-26: CAN Global Automatic Block Transmission Delay Register (CnGMABTD) Format Address R/W After reset see Table...
Page 594 Chapter 16 FCAN Controller CAN module mask control register (CnMASKaL, CnMASKaH) (a = 1, 2, 3, or 4) The CnMASKaL and CnMASKaH registers are used to extend the number of receivable mes- sages by masking part of the identifier (ID) of a message and invalidating the ID of the masked part.
Page 595 Chapter 16 FCAN Controller Figure 16-27: CAN Module Mask Control Register (CnMASKaL, CnMASKaH) (a = 1, 2, 3, or 4) Format (2/2) • CANn module mask 4 register (CnMASK4L, CnMASK4H) Address R/W After reset CnMASK4L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 R/W undefined see Table...
Page 596 Chapter 16 FCAN Controller CAN module control register (CnCTRL) The CnCTRL register is used to control the operation mode of the CAN module. Figure 16-28: CAN Module Control Register (CnCTRL) Format (1/4) (a) Read Address R/W After reset CnCTRL RSTAT TSTAT 0000H see Table...
Page 597 Chapter 16 FCAN Controller Figure 16-28: CAN Module Control Register (CnCTRL) Format (2/4) TSTAT Transmission status bit Transmission is stopped. Transmission is in progress. Remarks: 1. The TSTAT bit is set to 1 under the following conditions (timing): - The SOF bit of a transmit frame is detected - The first bit of an error flag is detected during a transmit frame 2.
Page 598 Chapter 16 FCAN Controller Figure 16-28: CAN Module Control Register (CnCTRL) Format (3/4) VALID Valid receive message frame detection bit A valid message frame has not been received since the VALID bit was last cleared to 0. A valid message frame has been received since the VALID bit was last cleared to 0. Remarks: 1.
Page 599 Chapter 16 FCAN Controller Figure 16-28: CAN Module Control Register (CnCTRL) Format (4/4) (b) Write Set AL Clear AL Setting of AL bit AL bit is cleared to 0. AL bit is set to 1. Other than above AL bit is not changed. Clear VALID Setting of VALID bit VALID bit is not changed.
Page 600 Chapter 16 FCAN Controller CAN module last error information register (CnLEC) The CnLEC register provides the error information of the CAN protocol. Figure 16-29: CAN Module Last Error Information Register (CnLEC) Format Address R/W After reset see Table CnLEC LEC2 LEC1 LEC0 16-16...
Page 601 Chapter 16 FCAN Controller CAN module information register (CnINFO) The CnINFO register indicates the status of the CAN module. Figure 16-30: CAN Module Information Register (CnINFO) Format Address R/W After reset see Table CnINFO BOFF TECS1 TECS0 RECS1 RECS0 16-16 BOFF Bus-off status bit Not bus-off state (transmit error counter £...
Page 602 Chapter 16 FCAN Controller CAN module error counter register (CnERC) The CnERC register indicates the count value of the transmission/reception error counter. Figure 16-31: CAN Module Error Counter Register (CnERC) Format Address R/W After reset CnERC REPS REC6 REC5 REC4 REC3 REC2 REC1...
Page 603 Chapter 16 FCAN Controller (10) CAN module interrupt enable register (CnIE) The CnIE register is used to enable or disable the interrupts of the CAN module. Figure 16-32: CAN Module Interrupt Enable Register (CnIE) Format (1/2) (a) Read Address R/W After reset CnIE see Table 16-16...
Page 604 Chapter 16 FCAN Controller Figure 16-32: CAN Module Interrupt Enable Register (CnIE) Format (2/2) (b) Write Set CIE3 Clear CIE3 Setting of CIE3 bit CIE3 bit is cleared to 0. CIE3 bit is set to 1. Other than above CIE3 bit is not changed. Set CIE2 Clear CIE2 Setting of CIE2 bit...
Page 605 Chapter 16 FCAN Controller (11) CAN module interrupt status register (CnINTS) The CnINTS register indicates the interrupt status of the CAN module. Figure 16-33: CAN Module Interrupt Status Register (CnINTS) Format (1/2) (a) Read Address R/W After reset CnINTS see Table 16-16 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 (b) Write...
Page 606 Chapter 16 FCAN Controller Figure 16-33: CAN Module Interrupt Status Register (CnINTS) Format (2/2) (b) Write Clear Setting of CINTS5 to CINTS0 bits CINTS5 to CINTS0 CINTS5 to CINTS0 bits are not changed. CINTS5 to CINTS0 bits are cleared to 0. (12) CAN module bit rate prescaler register (CnBRP) The CnBRP register is used to select the CAN protocol layer base clock (f ).
Page 607 Chapter 16 FCAN Controller Figure 16-35: CAN Module Clock CAN module clock selection register (CnGMCS) CCP3 CCP2 CCP1 CCP0 CANMOD CAN bit-rate Prescaler Baud rate generator register (CnBTR) TQPRS2 TQPRS1 TQPRS5 TQPRS4 TQPRS3 TQPRS0 TQPRS7 TQPRS6 CAN module bit-rate prescaler register (CnBRP) Remark: Clock supplied to CAN = f : CAN module system clock...
Page 608 Chapter 16 FCAN Controller (13) CAN module bit rate register (CnBTR) The CnBTR register is used to control the data bit time of the communication baud rate. Figure 16-36: CAN Module Bit Rate Register (CnBTR) Format (1/2) Address R/W After reset CnBTR SJW1 SJW0...
Page 609 Chapter 16 FCAN Controller Figure 16-36: CAN Module Bit Rate Register (CnBTR) Format (2/2) TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 Setting prohibited Note Note 10TQ 11TQ 12TQ 13TQ 14TQ 15TQ 16TQ (default value) Note: This setting must not be made when the CnBRP register = 00H. Remark: TQ = 1/f : CAN protocol layer basic system clock)
Page 610 Chapter 16 FCAN Controller (14) CAN module last in-pointer register (CnLIPT) The CnLIPT register indicates the number of the message buffer in which a data frame or a remote frame was last stored. Figure 16-37: CAN Module Last In-Pointer Register (CnLIPT) Format Address R/W After reset see Table CnLIPT...
Page 611 Chapter 16 FCAN Controller (15) CAN module receive history list register (CnRGPT) The CnRGPT register is used to read the receive history list. Figure 16-38: CAN Module Receive History List Register (CnRGPT) Format (1/2) (a) Read Address R/W After reset CnRGPT RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2 RGPT1 RGPT0 xx02H...
Page 612 Chapter 16 FCAN Controller Figure 16-38: CAN Module Receive History List Register (CnRGPT) Format (2/2) (b) Write Clear ROVF Setting of ROVF bit ROVF bit is not changed. ROVF bit is cleared to 0. (16) CAN module last out-pointer register (CnLOPT) The CnLOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last.
Page 613 Chapter 16 FCAN Controller (17) CAN module transmit history list register (CnTGPT) The CnTGPT register is used to read the transmit history list. Figure 16-40: CAN Module Transmit History List Register (CnTGPT) Format (1/2) (a) Read Address R/W After reset CnTGPT TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2 TGPT1 TGPT0 xx02H...
Page 614 Chapter 16 FCAN Controller Figure 16-40: CAN Module Transmit History List Register (CnTGPT) Format (2/2) (b) Write Clear TOVF Setting of TOVF bit TOVF bit is not changed. TOVF bit is cleared to 0. (18) CAN module time stamp register (CnTS) The CnTS register is used to control the time stamp function.
Page 615 Chapter 16 FCAN Controller Figure 16-41: CAN Module Time Stamp Register (CnTS) Format (2/2) TSSEL Time stamp capture event selection bit The time capture event is SOF. The time stamp capture event is the last bit of EOF. TSEN TSOUT operation setting bit TSOUT toggle operation is disabled.
Page 616 Chapter 16 FCAN Controller (19) CAN message data byte register (CnMDATAxm) (x = 0 to 7) The CnMDATAxm register is used to store the data of a transmit/receive message. Figure 16-42: CAN Message Data Byte Register (CnMDATAxm) (x = 0 to 7) Format (1/2) Address R/W After reset MDATA01...
Page 617 Chapter 16 FCAN Controller Figure 16-42: CAN Message Data Byte Register (CnMDATAxm) (x = 0 to 7) Format (2/2) Address R/W After reset MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 CnMDATA45m R/W undefined see Table 16-16 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45...
Page 618 Chapter 16 FCAN Controller (20) CAN message data length register m (CnMDLCm) The CnMDLCm register is used to set the number of bytes of the data field of a message buffer. Figure 16-43: CAN Message Data Length Register m (CnMDLCm) Format Address R/W After reset see Table CnMDLCm...
Page 619 Chapter 16 FCAN Controller (21) CAN message configuration register (CnMCONFm) The CnMCONFm register is used to specify the type of the message buffer and to set a mask. Figure 16-44: CAN Message Configuration Register (CnMCONFm) Format (1/2) Address R/W After reset see Table CnMCONFm OWS R/W undefined...
Page 620 Chapter 16 FCAN Controller Figure 16-44: CAN Message Configuration Register (CnMCONFm) Format (2/2) Message buffer assignment bit Message buffer not used. Message buffer used. Caution: Be sure to write 0 to bits 2 and 1. (22) CAN message ID register m (CnMIDLm, CnMIDHm) The CnMIDLm and CnMIDHm registers are used to set an identifier (ID).
Page 621 Chapter 16 FCAN Controller (23) CAN message control register m (CnMCTRLm) The CnMCTRLm register is used to control the operation of the message buffer. Figure 16-46: CAN Message Control Register m (CnMCTRLm) Format (1/3) (a) Read Address R/W After reset CnMCTRLm see Table 00x000000...
Page 622 Chapter 16 FCAN Controller Figure 16-46: CAN Message Control Register m (CnMCTRLm) Format (2/3) Message buffer data update bit A data frame or remote frame is not stored in the message buffer. A data frame or remote frame is stored in the message buffer. Message buffer transmission request bit No message frame transmitting request that is pending or being transmitted is in the message buffer.
Page 623 Chapter 16 FCAN Controller Figure 16-46: CAN Message Control Register m (CnMCTRLm) Format (3/3) Set TRQ Clear TRQ Setting of TRQ bit TRQ bit is cleared to 0. TRQ bit is set to 1. Other than above TRQ bit is not changed. Set RDY Clear RDY Setting of RDY bit...
Page 624: Bit Set/Clear Function
Chapter 16 FCAN Controller 16.7 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
Page 625 Chapter 16 FCAN Controller Figure 16-47: Example of Bit Setting/Clearing Operations 12 11 10 15 14 13 Register’s current value 15 14 13 12 11 10 Write value clear 1 15 14 13 12 11 10 Register’s value after write operation Figure 16-48: Bit Status After Bit Setting/Clearing Operations Clear Clear...
Page 626: Can Controller Initialization
Chapter 16 FCAN Controller 16.8 CAN Controller Initialization 16.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the CnGMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.
Page 627: Transition From Initialization Mode To Operation Mode
Chapter 16 FCAN Controller Figure 16-49: Setting Transmission Request (TRQ) to Transmit Message Buffer After Redefinition Redefinition completed Execute transmission? Wait for 1 bit of CAN data. Set TRQ bit Set TRQ bit = 1 Clear TRQ bit = 0 Cautions: 1.
Page 628: Resetting Error Counter Cnerc Of Can Module
Chapter 16 FCAN Controller Figure 16-50: Transition to Operation Modes OPMODE[2:0] = 00H and CAN bus is busy. [Receive-only mode] OPMODE[2:0]=03H OPMODE[2:0] = 00H OPMODE[2:0] = 00H and CAN bus is busy. and CAN bus is busy. [Normal operation OPMODE[2:0] = 03H mode with ABT] [Single-shot mode] OPMODE[2:0]=02H...
Page 629: Message Reception
Chapter 16 FCAN Controller 16.9 Message Reception 16.9.1 Message reception In all the operation modes, when a message is received, a message buffer that is to store the message is searched from all the message buffers satisfying the following conditions. •...
Page 630: Receive History List Function
Chapter 16 FCAN Controller 16.9.2 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive mes- sage buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corre- sponding CnLIPT register and the receive history list get pointer (RGPT) with the corresponding CnRGPT register.
Page 631 Chapter 16 FCAN Controller Figure 16-51: Receive History List Receive history list (RHL) Receive history list (RHL) Event: - Message buffer 6, 9, 2, and 7 are read by host processor. - Newly received messages are stored in message buffer Message buffer 8 3, 4, and 8.
Page 632: Mask Function
Chapter 16 FCAN Controller 16.9.3 Mask function It can be defined whether masking of the identifier that is set to a message buffer is linked with another message buffer. By using the mask function, the identifier of a message received from the CAN bus can be compared with the identifier set to a message buffer in advance.
Page 633 Chapter 16 FCAN Controller <3> Mask setting for CAN module 1 (mask 1) (Example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 CMID6...
Page 634: Multi Buffer Receive Block Function
Chapter 16 FCAN Controller 16.9.4 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type.
Page 635: Remote Frame Reception
Chapter 16 FCAN Controller 16.9.5 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. •...
Page 636: Message Transmission
Chapter 16 FCAN Controller 16.10 Message Transmission 16.10.1 Message transmission In all the operation modes, if the TRQ bit is set to 1 in a message buffer that satisfies the following con- ditions, the message buffer that is to transmit a message is searched. •...
Page 637 Chapter 16 FCAN Controller Priority Conditions Description The message frame with the lowest value represented by the first 11 bits Value of first 11 bits of ID of the ID is transmitted first. If the value of an 11-bit standard ID is equal to 1 (high) [ID28 to ID18]: or smaller than the first 11 bits of a 29-bit extended ID, the 11-bit standard...
Page 638: Transmit History List Function
Chapter 16 FCAN Controller 16.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer in which each data frame or remote frame was received and stored. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding CnLOPT register, and the transmit history list get pointer (TGPT) with the corresponding CnTGPT register.
Page 639: Automatic Block Transmission (Abt)
Chapter 16 FCAN Controller Figure 16-53: Transmit History List Transmit history list (THL) Transmit history list (THL) Event: Message buffer 4 - CPU confirms Tx completion Message buffer 3 of message buffer 6, 9, and 2. Last out- Message buffer 7 Last out- Message buffer 7 - Tx completion of message...
Page 640 Chapter 16 FCAN Controller During ABT, the priority of the transmission ID is not searched. The data of message buffers 0 to 7 is sequentially transmitted. When transmission of the data frame from message buffer 7 has been com- pleted, the ABTTRG bit is automatically cleared to 0 and the ABT operation is finished. If the RDY bit of an ABT message buffer is cleared during ABT, no data frame is transmitted from that buffer, ABT is stopped, and the ABTTRG bit is cleared.
Page 641: Transmission Abort Process
Chapter 16 FCAN Controller 16.10.4 Transmission abort process Transmission abort in normal operation mode The user can clear the TRQ bit of the CnMCTRLm register to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or not can be checked using the TSTAT bit of the CnCTRL register and the CnTGPT register, which indicate the transmission status on the CAN bus (for details, refer to the processing in Figure 16-66, “Transmission via Software Polling,”...
Page 642: Power Saving Modes
Chapter 16 FCAN Controller 16.11 Power Saving Modes 16.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN controller to standby mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered.
Page 643 Chapter 16 FCAN Controller (c) No transmission request is pending If any one of the conditions mentioned above is not met, the CAN module will operate as follows. • If the CAN sleep mode is requested from the initialization mode, the CAN sleep mode transition request is ignored and the CAN module remains in the initialization mode.
Page 644: Can Stop Mode
Chapter 16 FCAN Controller Releasing CAN sleep mode The CAN sleep mode is released by the following events. • When the CPU writes 00B to the PSMODE[1:0] bits of the CnCTRL register • A falling edge at the CAN reception pin (CRXDn) (i.e. the CAN bus level shifts from recessive to dominant) Caution: Even if the falling edge belongs to the SOF of a receive message, this message will...
Page 645 Chapter 16 FCAN Controller Status in CAN stop mode • The CAN module is in one of the following states after it enters the CAN stop mode. • The internal operating clock is stopped and the power consumption is minimized. •...
Page 646: Example Of Using Power Saving Modes
Chapter 16 FCAN Controller 16.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving sta- tus by the CAN bus.
Page 647: Interrupt Function
Chapter 16 FCAN Controller 16.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that cor- responds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.
Page 648: Diagnosis Functions And Special Operational Modes
Chapter 16 FCAN Controller 16.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 16.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes.
Page 649: Single-Shot Mode
Chapter 16 FCAN Controller In the receive-only mode, no message frames can be transmitted from the CAN module to the CAN bus. Transmit requests issued for message buffers defined as transmit message buffers are held pend- ing. In the receive-only mode, the CAN transmission pin (CTXDn) in the CAN module is fixed to the reces- sive level.
Page 650: Self-Test Mode
Chapter 16 FCAN Controller 16.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back.
Page 651: Time Stamp Function
Chapter 16 FCAN Controller 16.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autono- mous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchro- nous and may even have different frequencies).
Page 652: Baud Rate Settings
Chapter 16 FCAN Controller 16.15 Baud Rate Settings 16.15.1 Bit rate setting conditions Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller, as follows. (a) 5TQ ≤ SPT (sampling point) ≤ 17 TQ SPT = TSEG1 + 1 (b) 8 TQ ≤...
Page 653: Table 16-21: Settable Bit Rate Combinations
Chapter 16 FCAN Controller Table 16-21 shows the combinations of bit rates that satisfy the above conditions. Table 16-21: Settable Bit Rate Combinations (1/3) CnBTR Register Setting Valid Bit Rate Setting Sampling Value Point Unit SYNC PROP PHASE PHASE DBT Length TSEG1[3:0] TSEG2[2:0] SEGMENT...
Page 654 Chapter 16 FCAN Controller Table 16-21: Settable Bit Rate Combinations (2/3) CnBTR Register Setting Valid Bit Rate Setting Sampling Value Point Unit SYNC PROP PHASE PHASE DBT Length TSEG1[3:0] TSEG2[2:0] SEGMENT SEGMENT SEGMENT1 SEGMENT2 1001 64.7 1010 70.6 1011 76.5 1100 82.4 1101...
Page 655 Chapter 16 FCAN Controller Table 16-21: Settable Bit Rate Combinations (3/3) CnBTR Register Setting Valid Bit Rate Setting Sampling Value Point Unit SYNC PROP PHASE PHASE DBT Length TSEG1[3:0] TSEG2[2:0] SEGMENT SEGMENT SEGMENT1 SEGMENT2 0100 60.0 0101 70.0 0110 80.0 0111 90.0 0100...
Page 656: Representative Examples Of Baud Rate Settings
Chapter 16 FCAN Controller 16.15.2 Representative examples of baud rate settings Tables 16-22 and 16-23 show representative examples of baud rate settings. Table 16-22: Representative Examples of Baud Rate Settings (f = 8 MHz) (1/2) CANMOD CnBTR Register Set Baud Valid Bit Rate Setting (Unit: kbps) Setting Value Rate...
Page 657 Chapter 16 FCAN Controller Table 16-22: Representative Examples of Baud Rate Settings (f = 8 MHz) (2/2) CANMOD CnBTR Register Set Baud Valid Bit Rate Setting (Unit: kbps) Setting Value Rate Division CnBRP Sampling Value Ratio of Register Point SYNC PROP PHASE PHASE...
Page 658: Table 16-23: Representative Examples Of Baud Rate Settings (F Canmod = 16 Mhz)
Chapter 16 FCAN Controller Table 16-23: Representative Examples of Baud Rate Settings (f = 16 MHz) (1/2) CANMOD CnBTR Register Set Baud Valid Bit Rate Setting (Unit: kbps) Setting Value Rate Division CnBRP Sampling Value Ratio of Register Point SYNC PROP PHASE PHASE...
Page 659 Chapter 16 FCAN Controller Table 16-23: Representative Examples of Baud Rate Settings (f = 16 MHz) (2/2) CANMOD CnBTR Register Set Baud Valid Bit Rate Setting (Unit: kbps) Setting Value Rate Division CnBRP Sampling Value Ratio of Register Point SYNC PROP PHASE PHASE...
Page 660: Operation Of Can Controller
Chapter 16 FCAN Controller 16.16 Operation of CAN Controller Remark: n = 0, 1 m = 0 to 31 Figure 16-57: Initialization START CnGMCS register. CnGMCTRL register (Set GOM = 1). CnBRP register, CnBTR register. CnIE register. CnMASK register. Initialize message buffers.
Page 661 Chapter 16 FCAN Controller Figure 16-58: Re-initialization START Clear OPMODE. INIT mode? CnBRP register, CnBTR register. Initialize message buffers. CnIE register. CnERC and CnINFO register clear? CnMASK register. Set CCERC bit. Set CCERC = 1 Clear CCERC = 0 Set CnCTRL register. (Set OPMODE) Caution: After setting the CAN module to the initialization mode, avoid setting the module to...
Page 662 Chapter 16 FCAN Controller Figure 16-59: Message Buffer Initialization START RDY = 1? Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY = 0? CnMCONFm register CnMIDHm register CnMIDLm register Transmit message buffer? CnMDLCm register Clear CnMDATAm register.
Page 663 Chapter 16 FCAN Controller Figure 16-60 shows the processing for a receive message buffer (MT[2:0] bits of CnMCONFm register = 001B to 101B). Figure 16-60: Message Buffer Redefinition START Clear VALID bit CnCTRLCLEAR_VALID =1 RDY = 1? Clear RDY bit CnMCTRLm.SET_RDY = 0 CnMCTRLm.CLEAR_RDY = 1 RDY = 0?
Page 664 Chapter 16 FCAN Controller Transmitting message buffer redefinition in the following according to cases, perform processing trans- mitting message buffer redefinition flow. Figure 16-61: Transmitting Message Buffer Redefinition START Transmit abort process Clear RDY bit CnMCTRLm.SET_RDY = 0 CnMCTRLm.CLEAR_RDY = 1 RDY = 0? Data frame Remote frame...
Page 665 Chapter 16 FCAN Controller Figure 16-62 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B). Figure 16-62: Message Transmit Processing (Normal Operation Mode) START TRQ = 0? Clear RDY bit CnMCTRLm.SET_RDY = 0 CnMCTRLm.CLEAR_RDY = 1 RDY = 0? Data frame Remote frame...
Page 666 Chapter 16 FCAN Controller Figure 16-63 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B). Figure 16-63: Message Transmit Processing (Normal Operation Mode with ABT) START ABTTRG = 0? Clear RDY bit CnMCTRLm.SET_RDY = 0 CnMCTRLm.CLEAR_RDY = 1 RDY = 0? Set CnMDATAxm register...
Page 667 Chapter 16 FCAN Controller Figure 16-64: Transmission via Interrupt (Using CnLOPT register) START Transmit completion interrupt processing Read CnLOPT register Clear RDY bit CnMCRTLm.SET_RDY = 0 CnMCRTLm.CLEAR_RDY = 1 RDY = 0? Data frame Remote frame Data frame or remote frame? Set CnMDATAxm register Set CnMDLCm register Set CnMDLCm register,...
Page 668 Chapter 16 FCAN Controller Figure 16-65: Transmission via Interrupt (Using CnTGPT Register) START Transmit completion interrupt processing Read CnTGPT register TOVF = 1? Clear TOVF bit CnTGPT.CLEAR_TOVF = 1 Clear RDY bit CnMCRTLm.SET_RDY = 0 CnMCRTLm.CLEAR_RDY = 1 RDY = 0? Data frame Remote frame Data frame or remote frame?
Page 669 Chapter 16 FCAN Controller Figure 16-66: Transmission via Software Polling START CINTS0 = 1? Clear CINTS0 bit CnINTS .CLEAR_CINTS0 = 1 Read CnTGPT register TOVF = 1? Clear TOVF bit CnTGPT .CLEAR_TOVF bit = 1 Clear RDY bit CnMCTRLm.SET_RDY = 0 CnMCTRLm.CLEAR_RDY = 1 RDY = 0? Data frame...
Page 670 Chapter 16 FCAN Controller Figure 16-67: Transmission Abort Processing (except Normal Operation Mode with ABT) START Clear TRQ bit CnMCTRLm.SET_TRQ = 0 CnMCTRLm.CLEAR_TRQ = 1 Wait for 11 CAN data bits TSTAT = 0? Read CnLOPT register Message buffer to be aborted matches CnLOPT register? Transmit abort request...
Page 671 Chapter 16 FCAN Controller In the normal operation with ABT, to abort transmit except transmission with ABT, using this processing flow. Figure 16-68: Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) START Clear ABTTRG bit CnGMABT.SET_ABTTRG = 0 CnGMABT.CLEAR_ABTTRG = 1 ABTTRG = 0? Clear TRQ bit...
Page 672 Chapter 16 FCAN Controller Figure 16-69 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 16-69: Transmission Abort Processing (Normal Operation Mode with ABT) START Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 ABTTRG = 0?
Page 673 Chapter 16 FCAN Controller Figure 16-70 shows the processing to not skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 16-70: Transmission Request Abort Processing (Normal Operation Mode with ABT) START Clear TRQ bit of message buffer undergoing transmission.
Page 674 Chapter 16 FCAN Controller Figure 16-71: Reception via Interrupt (Using CnLIPT Register) START Transmit abort Read CnLIPT register. Clear DN bit. Clear DN bit = 1 Read CnMDATAxm, CnMDLCm, CnMIDLm, and CnMIDHm registers. DN = 0 and Note MUC = 0 Clear CINTS1 bit.
Page 675 Chapter 16 FCAN Controller Figure 16-72: Reception via Interrupt (Using CnRGPT Register) START Receive completion interrupt Read CnRGPT register. ROVF = 1? Clear ROVF bit. Clear ROVF bit = 1 Clear DN bit. Clear DN bit = 1 DN = 0 and Note MUC = 0 Read CnMDATAxm, CnMDLCm,...
Page 676 Chapter 16 FCAN Controller Figure 16-73: Reception via Software Polling START CINTS1 = 1? ClearCINTS1 bit. Clear CINTS1 bit = 1 Read CnRGPT register. ROVF = 1? Clear ROVF bit. Clear ROVF bit = 1 Clear DN bit. Clear DN bit = 1 DN = 0 Note and MUC = 0...
Page 677 Chapter 16 FCAN Controller Figure 16-74: Setting CAN Sleep Mode/Stop Mode START (when PSMODE[1:0] = 00B) Set PSMODE0 bit CnCTRL.SET_PSMODE1 = 1 CnCTRL.CLEAR_PSMODE1 = 0 PSMODE0 = 1? CAN sleep mode Set PSMODE1 bit CnCTRL.SET_PSMODE1 = 1 CnCTRL.CLEAR_PSMODE1 = 0 PSMODE1 = 1? Request CAN sleep mode again?
Page 678 Chapter 16 FCAN Controller Figure 16-75: Clear CAN Sleep/Stop Mode START CAN stop mode Clear PSMODE1 bit. Set PSMODE1 bit = 0 Clear PSMODE1 bit = 1 Releasing CAN sleep mode CAN sleep mode by CAN bus active Releasing CAN sleep mode by user Bus activity = 0 PSMODE0 = 0...
Page 679 Chapter 16 FCAN Controller Figure 16-76: Bus-Off Recovery START BOFF = 1? Set CnCTRL register. (Clear OPMODE) INIT mode? Access to register other than CnCTRL and CnGMCTRL registers Forced recovery from bus off? Set CCERC bit. Set CnCTRL register. Set CCERC bit = 1 (Set OPMODE) Clear CCERC bit = 0 Set CnCTRL register.
Page 680 Chapter 16 FCAN Controller Figure 16-77: Normal Shutdown Process START IINIT mode Clear GOM bit. Set GOM bit = 0 Clear GOM bit = 1 GOM = 0? Shutdown successful GOM = 0, EFSD = 0 Figure 16-78: Forced Shutdown Process START Set EFSD bit.
Page 681 Chapter 16 FCAN Controller Figure 16-79: Error Handling START Error interrupt CINTS2 = 1? Check CAN module state. (read CnINFO register) Clear CINTS2 bit. Clear CINTS2 bit = 1 CINTS3 = 1? CINTS4 = 1? Check CAN protocol error state. (Read CnLEC register) Clear CINTS4 bit.
Page 682 Chapter 16 FCAN Controller Figure 16-80: Setting CPU Standby (from CAN Sleep Mode) START Set PSMODE0 bit. CnCTRL.SET_PSMODE0 = 1 CnCTRL.CLEAR_PSMODE0 = 0 PSMODE0 bit = 1 ? CAN sleep mode Enable interrupts Disable interrupts PSMODE[1:0] bits = 01B ? Set CPU standby mode.
Page 683 Chapter 16 FCAN Controller Figure 16-81: Setting CPU Standby (from CAN Stop Mode) START Set PSMODE0 bit. CnCTRL.SET_PSMODE0 = 1 CnCTRL.CLEAR_PSMODE0 = 0 PSMODE0 = 1? Clear CINTS5 bit. Note CnINTS.CLEAR_CINTS5 = 1 CAN sleep mode Set PSMODE1 bit. CnCTRL.SET_PSMODE0 = 1 CnCTRL.CLEAR_PSMODE0 = 0 PSMODE1 = 1 ? CAN stop mode...
Page 684 [MEMO] User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 685: Chapter 17 Interrupt/Exception Processing Function
Chapter 17 Interrupt/Exception Processing Function The V850E/RS1 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 69 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 686 Chapter 17 Interrupt/Exception Processing Function Table 17-1: Interrupt/Exception Source List (2/3) Interrupt Classifica- Default Generating Exception Handler Restored Type Name Trigger Control tion Priority Unit Code Address Register Maskable Interrupt INTP5 INTP5 pin valid edge input PORT 00E0H 000000E0H nextPC PIC5 Maskable Interrupt INTP6 INTP6 pin valid edge input...
Page 687 Chapter 17 Interrupt/Exception Processing Function Table 17-1: Interrupt/Exception Source List (3/3) Interrupt Classifica- Default Generating Exception Handler Restored Type Name Trigger Control tion Priority Unit Code Address Register Maskable Interrupt INTUA1T UARTA1 transfer completion UARTA1 02A0H 000002A0H nextPC UA1TIC Maskable Interrupt INTAD AD conversion completion 02B0H 000002B0H nextPC ADIC...
Page 688: Non-Maskable Interrupts
Chapter 17 Interrupt/Exception Processing Function 17.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts. This product has the following two non-maskable interrupts.
Page 689 Chapter 17 Interrupt/Exception Processing Function Figure 17-1: Non-Maskable Interrupt Request Acknowledgement Operation (2/2) (b) Non-maskable interrupt request generated during non-maskable interrupt servicing Non-maskable Non-maskable interrupt request signal generated during non-maskable interrupt servicing interrupt being INTWDT2 servicing • NMI request generated during NMI servicing •...
Page 690: Operation
Chapter 17 Interrupt/Exception Processing Function 17.2.1 Operation If a non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 691: Restore
Chapter 17 Interrupt/Exception Processing Function 17.2.2 Restore From NMI Execution is restored from the NMI by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 692: Np Flag
Chapter 17 Interrupt/Exception Processing Function 17.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is under execution. This flag is set when a non-maskable interrupt request has been acknowledged, and masks non-mask- able interrupt requests to prohibit multiple interrupts from being acknowledged. Figure 17-4: NP Flag Format After reset: 00000020H NP EP...
Page 693: Function To Detect Edge Of Nmi Pin
Chapter 17 Interrupt/Exception Processing Function 17.2.5 Function to detect edge of NMI pin The valid edge of the NMI pin can be selected from three types: “rising edge”, “falling edge”, and “both edges”. Specify the valid edge of the non-maskable interrupt (NMI) by using the NMI mode register (NMIM). This register can be read or written in only 8-bit units, and can be written only once after each RESET condition.
Page 694: Maskable Interrupts
Chapter 17 Interrupt/Exception Processing Function 17.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850E/RS1 has 59 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 695 Chapter 17 Interrupt/Exception Processing Function Figure 17-6: Maskable Interrupt Servicing INT input INTC accepted xxIF = 1 Interrupt requested? xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 696: Restore
Chapter 17 Interrupt/Exception Processing Function 17.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1>...
Page 697: Priorities Of Maskable Interrupts
Chapter 17 Interrupt/Exception Processing Function 17.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 698 Chapter 17 Interrupt/Exception Processing Function Figure 17-8: Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 699 Chapter 17 Interrupt/Exception Processing Function Figure 17-8: Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 700 Chapter 17 Interrupt/Exception Processing Function Figure 17-9: Example of Servicing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 701: Interrupt Control Register (Xxicn)
Chapter 17 Interrupt/Exception Processing Function 17.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Figure 17-10: Interrupt Control Register (xxICn) Format After reset: 47H Address: FFFFF110H to FFFFF18EH...
Page 702: Table 17-2: Interrupt Control Register (Xxicn) (1/2
Chapter 17 Interrupt/Exception Processing Function Table 17-2: Interrupt Control Register (xxICn) (1/2) Address Register <7> <6> FFFFF110H LVIIC LVIIF LVIMK LVIPR2 LVIPR1 LVIPR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2 PPR22 PPR21...
Page 703 Chapter 17 Interrupt/Exception Processing Function Table 17-2: Interrupt Control Register (xxICn) (2/2) Address Register <7> <6> FFFFF15EH C0TRXIC C0TRXIF C0TRXMK C0TRXPR2 C0TRXPR1 C0TRXPR0 FFFFF160H C30IC C30IF C30MK C30PR2 C30PR1 C30PR0 FFFFF162H C30OC C30OIF C30OMK C30OPR2 C30OPR1 C30OPR0 FFFFF164H C31IC C31IF C31MK C31PR2 C31PR1...
Page 704: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
Chapter 17 Interrupt/Exception Processing Function 17.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn bit of the xxICn register. The IMRm register can be read or written in 16-bit units (m = 0 to 3).
Page 705: In-Service Priority Register (Ispr)
Chapter 17 Interrupt/Exception Processing Function 17.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an inter- rupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 706: Maskable Interrupt Status Flag
Chapter 17 Interrupt/Exception Processing Function 17.3.7 Maskable interrupt status flag This flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. An interrupt disable flag (ID) is incorporated, which is assigned to the PSW. Figure 17-13: Maskable Interrupt Status Flag Format After reset: 00000021H NP EP...
Page 707: Watchdog Timer Mode Register 2 (Wdtm2)
Chapter 17 Interrupt/Exception Processing Function 17.3.8 Watchdog timer mode register 2 (WDTM2) This register is a special register and can be written only in a specific sequence. To generate a maska- ble interrupt (INTWDT2), clear the WDM20 bit of this register to 0. This register can be read or written in 8-bit or 1-bit units (for details, refer to Chapter 10 ”Functions of Watchdog Timer 2”...
Page 708: Eliminating Noise On Intp0 To Intp7 Pins
Chapter 17 Interrupt/Exception Processing Function Table 17-3: Watchdog Timer 2 Clock Selection Selected WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 100 kHz (MIN.) 200 kHz (TYP.) 400 kHz (MAX.) clock 41.0 ms 20.5 ms 10.2 ms 81.9 ms 41.0 ms 20.5 ms 163.8 ms 81.9 ms 41.0 ms...
Page 709: Table 17-4: Valid Edge Specification
Chapter 17 Interrupt/Exception Processing Function External interrupt falling edge specification register 0 (INTF0) This is an 8-bit register that specifies detection of the falling edge of the external interrupt pins. This register can be read or written in 8-bit or 1-bit units. Caution: When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected.
Page 710: Table 17-5: Valid Edge Specification
Chapter 17 Interrupt/Exception Processing Function External interrupt falling edge specification register 1 (INTF1) This is an 8-bit register that specifies detection of the falling edge of the external interrupt pins. This register can be read or written in 8-bit or 1-bit units. Caution: When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected.
Page 711: Table 17-6: Valid Edge Specification
Chapter 17 Interrupt/Exception Processing Function External interrupt falling edge specification register 3 (INTF3) This is an 8-bit register that specifies detection of the falling edge of the external interrupt pins. This register can be read or written in 8-bit or 1-bit units. Caution: When the function is changed from the external interrupt function (alternate func- tion) to the port function, an edge may be detected.
Page 712: Table 17-7: Valid Edge Specification
Chapter 17 Interrupt/Exception Processing Function External interrupt falling edge specification register 9H (INTF9H) This is an 8-bit register that specifies detection of the falling edge of the external interrupt pins. This register can be read or written in 8-bit or 1-bit units. Figure 17-21: External Interrupt Falling Edge Specification Register 9H (INTF9H) Format After reset: 00H Address: FFFFFC13H...
Page 713 Chapter 17 Interrupt/Exception Processing Function Noise elimination control register Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are per- formed with the NFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f /32, f /64, f...
Page 714: Software Exception
Chapter 17 Interrupt/Exception Processing Function 17.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 17.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 715: Restore
Chapter 17 Interrupt/Exception Processing Function 17.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. <2>...
Page 716: Exception Status Flag (Ep)
Chapter 17 Interrupt/Exception Processing Function 17.4.3 Exception status flag (EP) The EP flag is bit 6 of the PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Figure 17-26: Exception Status Flag (EP) Format After reset: 00000021H NP EP...
Page 717: Exception Trap
Chapter 17 Interrupt/Exception Processing Function 17.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. Therefore, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an excep- tion trap.
Page 718 Chapter 17 Interrupt/Exception Processing Function Figure 17-28: Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC Restored PC DBPSW PSW.NP PSW.EP PSW.ID 00000060H Exception processing Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored <1>...
Page 719 Chapter 17 Interrupt/Exception Processing Function 17.5.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. Upon occurrence of a debug trap, the CPU performs the following processing. Operation <1>...
Page 720 Chapter 17 Interrupt/Exception Processing Function Restoration Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW. <2>...
Page 721: Interrupt Acknowledge Time Of Cpu
Chapter 17 Interrupt/Exception Processing Function 17.6 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt requests successively, input the next interrupt at least 4 clocks after the preceding interrupt. •...
Page 722: Periods In Which Interrupts Are Not Acknowledged By Cpu
Chapter 17 Interrupt/Exception Processing Function 17.7 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending).
Page 723: Chapter 18 Standby Function
Chapter 18 Standby Function 18.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 18-1. Table 18-1: Standby Modes Mode Functional Outline...
Page 724: Status Transition
Chapter 18 Standby Function 18.2 Status Transition Figure 18-1: Status Transition RESET RING operation Note X1 Stabilization Each STBY (HALT/IDEL1/IDEL2/STOP PLL operation (PLL =ON) X1 through mode Each STBY (PLL =ON) (HALT/IDEL1/IDEL2/STOP) X1 through mode (PLL =OFF) Each STBY (HALT/IDEL1/IDEL2/STOP) Note: RING operation is executed when WDT2RES is generated during the oscillation stabilization time.
Page 725 Chapter 18 Standby Function Figure 18-2: Standby Transition from PLL Operation (PLL = ON) Note 2 PLL operation (PLL = ON) HALT mode STOP mode Note 1 X1 = ON, PLL = ON X1 = OFF, PLL = OFF IDLE1 mode IDLE2 mode X1 = ON, PLL = OFF X1 = ON, PLL = ON...
Page 726 Chapter 18 Standby Function Figure 18-4: Standby Transition from X1 Through Mode (PLL = OFF) Note 2 X1 through mode (PLL = OFF) STOP mode HALT mode Note 1 X1 = ON, PLL = OFF X1 = OFF, PLL = OFF IDLE1 mode IDLE2 mode X1 = ON, PLL = OFF...
Page 727: Halt Mode
Chapter 18 Standby Function 18.3 HALT Mode 18.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped, clock supply to the other on-chip peripheral functions continues.
Page 728: Table 18-3: Operation Status In Halt Mode
Chapter 18 Standby Function Releasing HALT mode by RESET pin input The same operation as the normal reset operation is performed. Table 18-3: Operation Status in HALT Mode Setting of HALT Mode Operation Status Item Main clock oscillator (f Oscillation enabled Ring clock generator (f Oscillation enabled Operable...
Page 729: Idle1 Mode
Chapter 18 Standby Function 18.4 IDLE1 Mode 18.4.1 Setting and operation status The IDLE1 mode is set by clearing the PSM1, 0 bit of the power save mode register (PSMR) to 00 and setting the STP bit of the power save control register (PSC) to 1 in the normal operation mode. In the IDLE1 mode, the clock oscillator, PLL and Flash continues operation but clock supply to the CPU and other on-chip peripheral functions stops.
Page 730: Table 18-4: Operation After Releasing Idle1 Mode By Interrupt Request
Chapter 18 Standby Function Table 18-4: Operation After Releasing IDLE1 Mode by Interrupt Request Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt Execution branches to the handler address request Execution branches to the handler Maskable interrupt address or the next instruction is The next instruction is executed.
Page 731: Idle2 Mode
Chapter 18 Standby Function 18.5 IDLE2 Mode 18.5.1 Setting and operation status The IDLE2 mode is set by clearing the PSM1, 0 bit of the power save mode register (PSMR) to 10 and setting the STP bit of the power save control register (PSC) to 1 in the normal operation mode. In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL and other on-chip peripheral functions stops.
Page 732: Table 18-6: Operation After Releasing Idle2 Mode By Interrupt Request
Chapter 18 Standby Function Table 18-6: Operation After Releasing IDLE2 Mode by Interrupt Request Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt Execution branches to the handler address after securing the prescribed setup time. request Execution branches to the handler Maskable interrupt address or the next instruction is The next instruction is executed after...
Page 733: Securing Setup Time When Releasing Idle2 Mode
Chapter 18 Standby Function 18.5.3 Securing setup time when releasing IDLE2 mode Secure the setup time for the ROM (flash memory) after releasing the IDLE2 mode because the operation of the blocks other than the main clock oscillator stops after IDLE2 mode is set. Releasing IDLE2 mode by non-maskable interrupt request or unmasked maskable interrupt request Secure the specified setup time by setting the OSTS register.
Page 734: Stop Mode
Chapter 18 Standby Function 18.6 STOP Mode 18.6.1 Setting and operation status The STOP mode is set when the PSM1, 0 bits of the PSMR register are set to 01 and the STP bit of the PSC register is set to 1 in the normal operation mode. In the STOP mode, the main clock oscillator stops.
Page 735: Table 18-8: Operation After Releasing Stop Mode By Interrupt Request
Chapter 18 Standby Function Table 18-8: Operation After Releasing STOP Mode by Interrupt Request Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt Execution branches to the handler address after securing the prescribed setup time. request Execution branches to the handler Maskable interrupt address or the next instruction is The next instruction is executed after...
Page 736: Securing Oscillation Stabilization Time
Chapter 18 Standby Function 18.7 Securing Oscillation Stabilization Time When the STOP mode is released, only the oscillation stabilization time set by the OSTS register elapses. If the STOP mode has been released by RESET pin input, however, the reset value of the OSTS register, 2 elapses.
Page 737: Control Registers
Chapter 18 Standby Function 18.8 Control Registers Power save control register (PSC) This is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the STOP mode. The PSC register is a special register (refer to 3.2.3 ”Special regis- ters”...
Page 738 Chapter 18 Standby Function Power save mode register (PSMR) This is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Figure 18-8: Power Save Mode Register (PSMR) Format Symbol Address...
Page 739: Chapter 19 Reset Function
Chapter 19 RESET Function 19.1 Overview The following reset functions are available. Five kinds of reset sources: • External reset input via the RESET pin • Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES) • System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected voltage (see Chapter 24 ”Low-Voltage Detector”...
Page 740: Registers To Check Reset Source
Chapter 19 RESET Function 19.2 Registers to Check Reset Source Reset source flag register (RESF) The RESF register indicates from which source a reset signal has been generated. This register is read-only, in 8-bit units. RESET input/POC reset clears this register to 00H. The default value differs if reset is effected from a source other than RESET.
Page 741: Operation
Other on-chip peripheral functions Operation stops oscillation stabilization time Note: Because the V850E/RS1 supports a boot swap function, the firmware uses part of the internal RAM after the internal system reset is released. Therefore, the contents of some areas (RAM...
Page 742 Chapter 19 RESET Function Figure 19-2: Timing of Reset Operation by RESET Pin Input × 4 Operation Initialized to Operation RESET Analog delay Analog delay Analog delay Analog delay (deleted as noise) (deleted as noise) Internal reset signal Count of oscillation Count of PLL oscillation stabilization time stabilization time...
Page 743: Reset Operation By Wdt2Res Signal
Other on-chip peripheral functions Operation stops oscillation stabilization time Note: Because the V850E/RS1 supports a boot swap function, the firmware uses part of the internal RAM after the internal system reset is released. Therefore, the contents of some areas (RAM...
Page 744 Chapter 19 RESET Function Figure 19-4: Timing of Reset Operation by WDT2RES Signal Generation × 4 Operation Initialized to f Operation WDTRES2 Analog delay Internal reset signal Analog delay Count of oscillation Count of PLL oscillation stabilization time stabilization time ×...
Page 745: Reset Operation By Low Voltage Detector And Power On Clear
Other on-chip peripheral functions Operation stops oscillation stabilization time Note: Because the V850E/RS1 supports a boot swap function, the firmware uses part of the internal RAM after the internal system reset is released. Therefore, the contents of some areas (RAM...
Page 746 Chapter 19 RESET Function Figure 19-5: Timing of Reset Operation by Low-Voltage Detector Power Supply (V LVI detection Voltage POC detection Voltage Time LVION Clear Delay Delay LVIOUTZ LVICRLZ LVIRESZ Delay POCRESZ Internal reset (Active Low) Notes: 1. The time period between a dashed line and the rising or falling edge of a control signal rep- resents the minimum analog delay in the circuit.
Page 747: Chapter 20 Regulator
Chapter 20 Regulator 20.1 Outline The V850E/RS1 has an on-chip regulator to lower the power consumption and noise. This regulator supplies a stepped-down V power supply voltage to the oscillator block and internal logic circuits (except the A/D converter and I/O buffer).
Page 748: Operation
Chapter 20 Regulator 20.2 Operation The regulator operates in all modes (Normal mode, HALT mode, IDLE1 mode, IDLE2 mode, STOP mode, and during RESET). Be sure to connect a capacitor (REGC0: 4.7 µF, REGC1: 1.0 µF) to the REGC0 and REGC1 pin to sta- bilize the regulator output.
Page 749: Chapter 21 Flash Memory
Flash memory is commonly used in the following development environments and applications. • For altering software after solder-mounting the V850E/RS1 on the target system • For differentiating software in small-scale production of various models.
Page 750: Erasure Unit
Chapter 21 Flash Memory 21.2 Erasure Unit The units in which the 256 or 128 KB flash memory can be erased are as follows. Chip erase The areas of xx000000H to xx01FFFFH and xx000000H to xx03FFFFH can be erased at the same time.
Page 751: Address Assignment In The Memory Map
Chapter 21 Flash Memory 21.2.1 Address assignment in the memory map Each block of the flash device is assigned to the address space of the internal ROM. Figure 21-1: Address Assignment of Flash Blocks for V850E/RS1 3FFFFH Block 7 - 56 KB...
Page 752: Writing With Flash Programmer
Mount a connector that connects the dedicated flash programmer on the target system. Off-board programming The flash memory of the V850E/RS1 can be written before the device is mounted on the target system, by using a dedicated program adapter (FA series).
Page 753: Communication Mode
Chapter 21 Flash Memory 21.5 Communication Mode Serial communication is performed between the dedicated flash programmer and the V850E/RS1 by using UARTA0 or CSIB0 of the V850E/RS1. UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 21-3: Communication with Dedicated Flash Programmer (UARTA0)
Page 754 RESET RESET SOB0 Dedicated flash SIB0 V850E/RS1 programmer SCKB0 Cautions: 1. Process the pins not shown in accordance with processing of unused pins (see 2.4 ”Pin I/O Circuit Types, I/O Buffer Power Supply and Handling of Unused Pins” on page 57). To connect a resistor, a resistor of 1 k to 10 Ω is recom- mended.
Page 755: Table 21-1: Signal Generation Of Dedicated Flash Programmer (Pg-Fp4)
Chapter 21 Flash Memory The dedicated flash programmer outputs the transfer clock, and the V850E/RS1 operates as a slave. When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850E/RS1. For details, refer to the PG-FP4 manual (U15260E).
Page 756: Pin Connection
Chapter 21 Flash Memory 21.6 Pin Connection A connector must be mounted on the target system to connect the dedicated flash programmer for on- board writing. In addition, a function to switch between the normal operation mode and flash memory programming mode must be provided on the board.
Page 757: Flmd1 Pin
Chapter 21 Flash Memory 21.6.2 FLMD1 pin If 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. If VDD is supplied to the FLMD0 pin, 0 V must be input to the FLMD1 pin to set the flash memory programming mode. An example of the connection of the FLMD1 pin is shown below.
Page 758: Serial Interface Pin
Chapter 21 Flash Memory 21.6.3 Serial interface pin The pins used by each serial interface are shown in the table below. Table 21-3: Pins Used by each Serial Interface Serial Interface Pins Used CSIB0 SOB0, SIB0, SCKB0 CSIB0 + HS SOB0, SIB0, SCKB0, PCM0 UARTA0 TXDA0, RXDA0...
Page 759 (input), a signal is output to the other device, causing a malfunction. To avoid this malfunction, isolate the connection with the other device, or set so that the other device ignores an input signal from V850E/RS1. Figure 21-9: Abnormal Operation of Other Device...
Page 760: Reset Pin
Chapter 21 Flash Memory 21.6.4 RESET pin When the reset signal of the dedicated flash programmer is connected to the RESET pin connected to a reset signal generator on board, a signal conflict occurs. To avoid this signal conflict, isolate the con- nection with the reset signal generator.
Page 761: Recommended Circuit Example Of The Flash Write Mode
21.7 Recommended Circuit Example of the Flash Write Mode Figure 21-11 shows the recommended circuit example of the flash write mode. Figure 21-11: Recommended Circuit Example RESET RESET SOB0/TXDA0 SIB0/RXDA0 SIB0/RXDA0 SOB0/TXDA0 V850E/RS1 Dedicated flash SCKB0 SCKB0 programmer FLMD0 FLMD0 FLMD1 FLMD1...
Page 762: Programming Method
Chapter 21 Flash Memory 21.8 Programming Method 21.8.1 Flash memory control The procedure to manipulate the flash memory is illustrated below. Figure 21-12: Procedure for Manipulating Flash Memory Start Switch to flash memory Supplies RESET pulse programming mode Select communication mode Manipulate flash memory End? User’s Manual U16702EE3V2UD00...
Page 763: Flash Memory Programming Mode
21.8.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the V850E/RS1 in the flash memory programming mode. To set the mode, set the FLMD0 and FLMD1 pins, and release reset.
Page 764: Selection Of Communication Mode
Chapter 21 Flash Memory 21.8.3 Selection of communication mode In the V850E/RS1, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
Page 765: Table 21-5: Flash Memory Control Command
√ Security setting command ure, and writing. The V850E/RS1 returns a response command in response to the command issued by the flash pro- grammer. The response commands sent by the V850E/RS1 are listed below. Table 21-6: Response Commands Response Command Name...
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Page 767: Chapter 22 On-Chip Debug Function
Chapter 22 On-Chip Debug Function The V850E/RS1 Series includes an on-chip debug unit. By connecting an N-Wire emulator, on-chip debugging can be executed with the V850E/RS1 microcontroller alone. Caution: The following debug functions are supported by the V850E/RS1 series, but whether they are usable or not differs depending on the debugger.
Page 768 Mask function Each signal can be masked. The correspondence with the mask functions of the debugger (ID850NWC) for the N-Wire emulator (IEV850E1-CD-NW) of NEC Electronics is shown below. - NMI0 mask function: – - NMI1 mask function: WDT2 interrupt - NMI2 mask function: NMI pin...
Page 769 Chapter 22 On-Chip Debug Function Figure 22-1: Block Diagram of On-chip Debug Function V850E/RS1 (V850E) On-chip debug unit Host machine N-Wire card (PC, EWS) User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 770: Security Function
22.2 Security Function The V850E/RS1 series have a security function that limits starting of the N-Wire emulator by comparing an ID code written in advance to the internal ROM area with an ID code that is input when the debugger is started, when the N-Wire emulator is connected.
Page 771: Control Register
Chapter 22 On-Chip Debug Function 22.3 Control Register On-chip debug mode register (OCDM) This register is used to select the normal operation mode or on-chip debug mode. This is a special register (refer to 3.2.3 ”Special registers” on page 70). It can be written only in a specific sequence so that its contents cannot be rewritten by mistake in the case of a program loop.
Page 772 Chapter 22 On-Chip Debug Function Configuration of Port 9 While the OCDM0 bit is set, the corresponding pins of Port 9 are configured to the on-chip debug mode and digital input/output cannot be performed. Also, the on-chip pull down resistor connected to P911/ DRST is likewise controlled by the PD9 control register, but this function may not be disabled while the OCDM0 bit is set.
Page 773: Operation Of On-Chip Debug Function
Chapter 22 On-Chip Debug Function 22.4 Operation of On-Chip Debug Function Figure 22-4: Timing Chart of Selecting Normal Operation Mode RESET (external reset input) (internal reset) OCDM0 DRST (on-chip debug reset input) Normal operation mode Normal operation mode Write 0 from CPU (to specify normal operation mode) Figure 22-5: Timing Chart of Selecting On-Chip Debug Mode To use the on-chip debug mode by using the power-on...
Page 774: Connection To N-Wire Emulator
22.5.1 KEL connector • Product name - 8830E-026-170S (KEL): Straight type - 8830E-026-170L (KEL): Right-angle type Figure 22-6: Connection to N-Wire Emulator (NEC Electronics IE-V850E1-CD-NW: N-Wire Card) Emulator connection connector 8830E-026-170S (KEL) N-Wire Card...
Page 775 Chapter 22 On-Chip Debug Function Pin configuration Figure 22-7 shows the pin configuration of the connector for emulator connection (target system side), and Table 22-2 shows the pin functions. Figure 22-7: Pin Configuration of Connector for Emulator Connection (Target System Side) B13 A13 B12 A12 Board side...
Page 776: Table 22-2: Pin Functions Of Connector For Emulator Connection (Target System Side)
– 5 V input (for monitoring power supply to target) Cautions: 1. The connection of the pins not supported by the V850E/RS1 series is dependent upon the emulator to be used. 2. The pattern of the target board must satisfy the following conditions.
Page 777 Chapter 22 On-Chip Debug Function Example of recommended circuit An example of the recommended circuit of the connector for emulator connection (target system side) is shown below. Figure 22-8: Example of Recommended Emulator Connection Circuit V850E/RS1 KEL connector 8830E-026-170S Note 3 (Reserved 1)
Page 778: Restrictions And Cautions On On-Chip Debug Function
Chapter 22 On-Chip Debug Function 22.6 Restrictions and Cautions on On-Chip Debug Function • Do not mount a device that was used for debugging on a mass-produced product (this is because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed).
Page 779: Chapter 23 Power-On-Clear Circuit
Chapter 23 Power-On-Clear Circuit 23.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V ) and detected voltage (V ), and generates internal reset signal when V <...
Page 780: Configuration Of Power-On-Clear Circuit
Chapter 23 Power-On-Clear Circuit 23.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 23-1. Figure 23-1: Block Diagram of Power-on-Clear Circuit Internal reset signal – Detection voltage source 23.3 Operation of Power-on-Clear Circuit The power-on-clear circuit compares the supply voltage (V ) and detected voltage (V ), and...
Page 781: Chapter 24 Low-Voltage Detector
Chapter 24 Low-Voltage Detector 24.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions: • Compares the supply voltage (V ) and detected voltage (V ), and generates an internal interrupt signal or internal reset signal when V <...
Page 782: Registers Controlling Low-Voltage Detector
Chapter 24 Low-Voltage Detector 24.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) Low-voltage detection register (LVIM) The LVIM register is a special register (see 3.2.3 ”Special registers” on page 70). It is used to enable or disable low-voltage detection and sets the operation mode of the low-voltage detector.
Page 783 Chapter 24 Low-Voltage Detector Low-voltage detection level selection register (LVIS) The LVIS register is used to select the level of low-voltage to be detected. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Figure 24-3: Low-Voltage Detection Level Selection Register (LVIS) Format Symbol Address...
Page 784 Chapter 24 Low-Voltage Detector Peripheral emulation register 1 (PEMU1) When an in-circuit emulator is used, the operation of the RAM retention flag (RAMF bit: bit 0 of RAMS register) can be pseudo-controlled and emulated by manipulating this register on the debugger.
Page 785: Operation Of Low-Voltage Detector
Chapter 24 Low-Voltage Detector 24.4 Operation of Low-Voltage Detector Depending on the setting of the LVIMD bit, an interrupt signal (INTLVI) or an internal reset signal is generated. How to specify each operation is described below, together with timing charts. 24.4.1 To use for internal reset signal <To start operation>...
Page 786 Chapter 24 Low-Voltage Detector Figure 24-6: Operation Timing of Low-Voltage Detector (LVIMD = 1) Supply voltage LVI detected voltage POC detected voltage Time Set (by instruction, refer Clear to <3> above.) (by POC reset request signal) LVION bit Delay Delay Delay Delay Delay...
Page 787 Chapter 24 Low-Voltage Detector 24.4.2 To use for interrupt <To start operation> <1> Mask the interrupt of LVI. <2> Select the voltage to be detected by using the LVIS0 bit. <3> Set the LVION bit to 1 (to enable operation). <4>...
Page 788: Ram Retention Voltage Detection Operation
Chapter 24 Low-Voltage Detector 24.5 RAM Retention Voltage Detection Operation The supply voltage and detected voltage are compared. When the supply voltage drops below the detected voltage (including on power application), the RAMF bit is set. Figure 24-8: Operation Timing of RAM Retention Voltage Detection Function Supply voltage POC detected voltage...
Page 789: Chapter 25 Clock Monitor
Chapter 25 Clock Monitor 25.1 Functions of Clock Monitor The clock monitor samples the main clock (X1 input clock) by using the on-chip Ring-OSC, and generates a reset request signal when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset.
Page 790: Register Controlling Clock Monitor
Chapter 25 Clock Monitor 25.3 Register Controlling Clock Monitor The Clock monitor is controlled by the clock monitor mode register (CLM). Clock monitor mode register (CLM) This register is used to set the operation mode of the clock monitor. This register can be read or written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 791: Operation Of Clock Monitor
Chapter 25 Clock Monitor 25.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The start and stop conditions are as follows. <Start condition> Enabling operation by setting bit 0 (CLME) of the clock monitor mode register to 1 <Stop condition>...
Page 792 Chapter 25 Clock Monitor Operation in software STOP mode or after software STOP mode is released If the software STOP mode is set with the CLME bit = 1, the monitor operation is stopped in the software STOP mode and while the oscillation stabilization time is being counted. After the oscilla- tion stabilization time, the monitor operation is automatically started.
Page 793: Chapter 26 Crc Function
Chapter 26 CRC Function 26.1 Functions • CRC operation circuit for detection of data block errors • Generation of 16-bit CRC code using a CRC-CCITT (X + 1) generation polynomial for blocks of data of any length in 8-bit units •...
Page 794: Registers
Chapter 26 CRC Function 26.3 Registers CRC input register (CRCIN) The CRCIN register is an 8-bit register for setting data. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Figure 26-2: CRC Input Register (CRCIN) Format Symbol Address After reset...
Page 795: Operation
Chapter 26 CRC Function 26.4 Operation An example of the CRC operation circuit is shown below. Figure 26-4: CRC Operation Circuit Operation Example (LSB First) (1) Setting of CRCIN = 01H (2) CRCD register read 1189H CRC code is stored The code when 01H is sent LSB first is (1000 0000).
Page 796: Usage Method
Chapter 26 CRC Function 26.5 Usage Method How to use the CRC operation circuit is described below. Figure 26-5: CRC Operation Flow Start Write of 0000H to CRCD register CRCIN register write Input data exists? CRCD register read [Basic usage method] <1>...
Page 797 Chapter 26 CRC Function Communication errors can easily be detected if the CRC code is transmitted/received along with trans- mit/receive data when transmitting/receiving data consisting of several bytes. The following is an illustration using the transmission of 12345678H (0001 0010 0011 0100 0101 0110 0111 1000B) LSB-first as an example.
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Page 799: Chapter 27 Electrical Specification
Chapter 27 Electrical Specification 27.1 General The following electrical specification characterizes the V850E/RS1. Unless noted otherwise, the data provided applies to all versions device (µPD70F3402, µPD70F3403, µPD70F3403A). Data that is unique to any of the versions will be indicated in the header of the subsection.
Page 800: Absolute Maximum Ratings (Μpd70F3402)
Chapter 27 Electrical Specification 27.2.1 Absolute maximum ratings (µPD70F3402) Parameter Symbol Condition Rating Unit Normal operation mode -40 to +110 °C Operating temperature Flash programming mode -40 to +85 °C 27.2.2 Absolute maximum ratings (µPD70F3403, µPD70F3403A) Parameter Symbol Condition Rating Unit Normal operation mode -40 to +85...
Page 801: Recommended Operating Conditions
Chapter 27 Electrical Specification 27.4 Recommended Operating Conditions 27.4.1 Recommended operating conditions (µPD70F3402) Digital Power Operating Ambient Analog Power Operation International Operating Supply (V Temperature (T Supply (AV Mode Clock Frequency REF0 , BV 24 MHz, 32 MHz Normal Mode REGC1: Capacity=4.7 µF -40°C to +110°C 4.0 V –...
Page 802: Oscillator Characteristics
Chapter 27 Electrical Specification 27.5 Oscillator Characteristics 27.5.1 General condition ≤ ≤ -40°C +110°C (µPD70F3402) ≤ ≤ -40°C +85°C (µPD70F3403, µPD70F3403A) =0 V ≤ ≤ ≤ 4.0 V 5.5 V 27.5.2 Oscillator timing and recommended oscillator connection Parameter Symbol Condition MIN.
Page 803: Voltage Regulator Characteristics
Chapter 27 Electrical Specification 27.6 Voltage Regulator Characteristics 27.6.1 General condition ≤ ≤ -40°C +110°C (µPD70F3402) ≤ ≤ -40°C +85°C (µPD70F3403, µPD70F3403A) =0 V 27.6.2 Regulator 0 Parameter Symbol Condition MIN. TYP. MAX. Unit After V reaches 4.0 V, Output voltage stabiliza- REG0 tion time C= 1.0 µF...
Page 804: Dc Characteristics
Chapter 27 Electrical Specification 27.7 DC Characteristics 27.7.1 General condition ≤ ≤ -40°C +110°C (µPD70F3402) ≤ ≤ -40°C +85°C (µPD70F3403, µPD70F3403A) ≤ ≤ 4.0 V 5.5 V ≤ ≤ 4.5 V 5.5 V REF0 =0 V 27.7.2 DC input/output level (1/2) Parameter Symbol...
Page 805 Chapter 27 Electrical Specification (2/2) Parameter Symbol Condition MIN. TYP. MAX. Unit Analog pins µA High-level output leakage current Other pins µA Analog pins µA Low-level output = 0 V leakage current Other pins µA Pull up kΩ Note 2 resistance Pull down kΩ...
Page 806: Dc Power Supply Current (Μpd70F3402)
Chapter 27 Electrical Specification 27.7.3 DC power supply current (µPD70F3402) Parameter Symbol Condition MIN. TYP. MAX. Unit PLL mode, f = 32 MHz Normal operation All functions are operating PLL mode, f = 32 MHz HALT mode All functions are operating PLL is on IDLE1 mode PLL is off...
Page 807: Ac Characteristics
Chapter 27 Electrical Specification 27.8 AC Characteristics 27.8.1 General condition ≤ ≤ -40°C +110°C (µPD70F3402) ≤ ≤ -40°C +85°C (µPD70F3403, µPD70F3403A) ≤ ≤ 4.0 V 5.5 V ≤ ≤ 4.5 V 5.5 V REF0 =0 V =50 pF 27.8.2 AC test input waveform Figure 27-3: AC Test Conditions , BV , AV...
Page 808: Input Waveform
Chapter 27 Electrical Specification 27.8.3 Input waveform Parameter Symbol Condition MIN. MAX. Unit Input rising time Input falling time Figure 27-4: Input Rise and Fall Time Input signal 27.8.4 Output waveform Parameter Symbol Condition MIN. MAX. Unit Output rising time Output falling time Figure 27-5: Output Rise and Fall Time Input signal...
Page 809: Reset, Nmi, Interrupt And Flmd0 Timing
Chapter 27 Electrical Specification 27.8.5 RESET, NMI, Interrupt and FLMD0 timing Parameter Symbol Condition MIN. MAX. Unit 500 + t When power supply is ON 500 + t When STOP mode is released RESET low level width WRSL Other than when power supply is ON nor STOP mode has been released NMI high level width...
Page 810: Timer P And Timer Q Input/Output
Chapter 27 Electrical Specification 27.8.6 Timer P and Timer Q input/output Parameter Symbol Conditions MIN. MAX. Unit TIPmn (m=0-3, n=0-1) TIQmn (m=0-1, n=0-3) Note Input high level width TOPmn (m=0-3, n=0-1) TOQmn (m=0-1, n=0-3) Note Input low level width Note: 2t + 20 or 3t + 20 (t is the noise reject sampling clock)
Page 811: Bus Interface Timing (Μpd70F3403, Μpd70F3403A Only)
Chapter 27 Electrical Specification 27.8.7 Bus interface timing (µPD70F3403, µPD70F3403A only) ≤ ≤ CLKOUT Asynchronous (4.5 V 5.5 V) Parameter Symbol Test Conditions MIN. MAX. Unit Address setting time (to ASTB↓) <14> 0.5T-10 SAST Address maintenance time (to ASTB↓) <15> 0.5T-10 HSTA RD↓...
Page 812 Chapter 27 Electrical Specification Figure 27-7: Read Cycle (CLKOUT Asynchronous, 1 Wait) CLKOUT (output) <17> Hi-z AD0 to AD15 (I/O) Address Data <14> <15> <20> ASTB (output) <25> <16> <22> <18> <21> <19> <23> RD (output) <24> <33> <35> <34> <36>...
Page 813 Chapter 27 Electrical Specification Figure 27-8: Write Cycle (CLKOUT Asynchronous, 1 WAIT) CLKOUT (output) AD0 to AD15 (I/O) Address Data <14> <15> ASTB (output) <25> <26> <22> <27> <28> <19> WR0 (output), WR1 (output) <24> <33> <35> <34> <36> WAIT (input) <29>...
Page 814 Chapter 27 Electrical Specification Figure 27-9: Bus Hold CLKOUT (output) <37> HLDRQ (intput) <42> <41> HLDAK (output) <40> <38> Hi-z Data AD0 to AD15 (I/O) Hi-z ASTB (outtput) Hi-z RD (output), WR0 (output), WR1 (output) User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 815: Csibn Timing
Chapter 27 Electrical Specification 27.8.8 CSIBn timing (a) Master mode Parameter Symbol Conditions MIN. MAX. Unit SCKBn cycle Output KCYM 0.5t SCKBn high-level width Output KWHM KCYMn 0.5t SCKBn low-level width Output KWLM KCYMn SIBn setup time (vs. SCKBn) SSIM SIBn hold time (vs.
Page 816: Uartan Timing
Chapter 27 Electrical Specification Figure 27-10: CSIBn Timing (CBnCKP=0, CBnDAP=0) KCYx KWLx KWHx SCKBn (I/O) HSIx SSIx Input data SIBn DSOx HSOx SOBn Output Remarks: 1. Broken line indicates high impedance. 2. “x” stands for either “M” (master mode) or “S” (slave mode) 27.8.9 UARTAn timing Parameter Symbol...
Page 817: Can Interface Timing (Μpd70F3402)
Chapter 27 Electrical Specification 27.8.10 CAN Interface timing (µPD70F3402) Parameter Symbol Conditions MIN. MAX. Unit CAN baud rate 83.333 kbps Internal transmit to receive data delay CTXDn CRXDn Remark: n = 0 27.8.11 CAN Interface timing (µPD70F3403, µPD70F3403A) Parameter Symbol Conditions MIN.
Page 818: Csi3N Timing
Chapter 27 Electrical Specification 27.8.13 CSI3n timing (a) Master mode: (SCK3n: output) Parameter Symbol MIN. MAX. Unit Macro operation clock cycle time KCY3 SCK3n cycle time KCY3M KWH3M 0.5t -10.0 SCK3n high, low width KCY3M KWL3M SI3n setup time (vs. SCK3n) 20.0 SSI3M SI3n hold time (vs.
Page 819 Chapter 27 Electrical Specification Figure 27-12: CSI3n Timings (1/2) (a) [SCK3n/SI3n/SO3n] pins in master mode: (CSIM:CKP/DAP=0/0 or 1/1) KCY3 Clock KSY3M KWL3M KWH3M SCK3n DSO3M HSO3M SO3n SSI3M HSI3M SI3n Remark: n = 0 to 1 (b) [SCK3n/SI3n/SO3n] pins in master mode: (CSIM:CKP/DAP=1/0 or 0/1) KCY3M KWH3M KWL3M...
Page 820 Chapter 27 Electrical Specification Figure 27-12: CSI3n Timings (2/2) (c) [SCK3n/SI3n/SO3n] pins slave mode: (CSIM:CKP/DAP=0/0 or 1/1) KCY3 Clock KCY3S KWL3S KWH3S SCK3n DSO3S HSO3S SO3n SSI3L HSI3S SI3n Remark: n = 0 to 1 (d) [SCK3n/SI3n/SO3n] pins in slave mode: (CSIM:CKP/DAP=1/0 or 0/1) KCY3S KWH3S KWL3S...
Page 821 Chapter 27 Electrical Specification Figure 27-13: CS3n3 - CS3n0 Pins Timings (1/3) (a) Only in master mode (CSIMn: CSIT = 0 & CSWE/CSMD = 0/0) Continuous transmission start SCK3n HSCSB0 SSCSB0 CS3n3 - CS3n0 INTCSIn Remark: n = 0 to 1 (b) Only in master mode (CSIMn: CSIT = 0 &...
Page 822 Chapter 27 Electrical Specification Figure 27-13: CS3n3 - CS3n0 Pins Timings (2/3) (c) Only in master mode (CSIMn: CSIT = 0 & CSWE/CSMD = 1/1) Continuous transmission start (SO output timing) SCK3n HSCSB0 WSCSB SSCSB0 CS3n3 - CS3n0 INTCSIn Remark: n = 0 to 1 (d) Only in Master mode, (CSIMn: CSIT = 1 &...
Page 823 Chapter 27 Electrical Specification Figure 27-13: CS3n3 - CS3n0 Pins Timings (3/3) (e) Only in Master mode, (CSIMn: CSIT = 1 & CSWE/CSMD = 1/0) Continuous transmission start (SO output timing) SCK3n HSCSB1 SSCSB1 CS3n3 - CS3n0 INTCSIn Remark: n = 0 to 1 (f) In Master mode, (CSIMn: CSIT = 1 &...
Page 824: A/D Converter Characteristics
Chapter 27 Electrical Specification 27.8.14 A/D Converter characteristics Parameter Symbol Condition MIN. TYP. MAX. Unit Resolution Total error ±3 Quantization error ±0.5 Conversion time µs CONV Recovery time from power-down µs mode Sampling error not Zero scale error ±2 included Sampling error not Full scale error ±2...
Page 825: Power-On-Clear (Poc)
Chapter 27 Electrical Specification 27.8.15 Power-on-clear (POC) Parameter Symbol Condition MIN. TYP. MAX. Unit Detection voltage POC0 Rise of V =0 V to V =3.5 V Supply voltage rise time 0.002 Timing at power-on condition Response time 1 PTHD after V reaches 3.9V Timing for power-down after Response time 2...
Page 826: Low-Voltage Indicator (Lvi)
Chapter 27 Electrical Specification 27.8.16 Low-Voltage Indicator (LVI) Parameter Symbol Condition MIN. TYP. MAX. Unit LVI0 Detection voltage LVI1 After V reached V (max.) LVI0/1 Response time 1 or dropped below V (min.) LVI0/1 drop minimum width After V reached the minimum Reference voltage stabili- operating voltage and LVION bit LWAIT...
Page 827: Power On Sequence
Chapter 27 Electrical Specification 27.9 Power on Sequence Figure 27-16: Power on Sequence RESET Main OSC RESET low level Boot process Application code executes width (t RSTL RESET Boot Total Low level PLL Factor Time Start-up Time width + 3.053 ms 8 MHz 32 MHz 1.024 ms...
Page 828: Flash Memory Characteristics
Chapter 27 Electrical Specification 27.10 Flash Memory Characteristics 27.10.1 General condition ≤ ≤ -40°C +110°C (µPD70F3402) ≤ ≤ -40°C +85°C (µPD70F3403, µPD70F3403A) ≤ ≤ 4.0 V 5.5 V ≤ ≤ 4.5 V 5.5 V REF0 =0 V =50 pF 27.10.2 Basic Flash characteristics (µPD70F3402) Parameter Symbol Condition...
Page 829: External Flash Programmer Serial Write Operation Characteristics
Chapter 27 Electrical Specification 27.10.4 External Flash programmer serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit FLMD0 setup time (from α Note 16581/f RFCF release of RESET signal) FLMD0 high level width µs FLMD0 low level width µs FLMD0 rise time FLMD0 fall time...
Page 830: Flash Programming Characteristics
Chapter 27 Electrical Specification 27.10.5 Flash programming characteristics Operating Parameter Conditions MIN. TYP. MAX. Unit frequency 8 KB =32 MHz Block erase 56 KB 3082 =32 MHz Write 256 bytes 8 KB 47.8 =32 MHz Block verification 56 KB 8 KB 22.2 =32 MHz Block blank check...
Page 831: Chapter 28 Package Drawing
Chapter 28 Package Drawing Figure 28-1: Package Drawing 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 16.00±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 16.00±0.20 1.00...
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Page 833: Chapter 29 Recommended Soldering Conditions
Chapter 29 Recommended Soldering Conditions V850E/RS1 should be soldered and mounted under the following recommended conditions. For soldering methods and condition other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the follow website: http://www.ee.nec.de 100-pin plastic LQFP (Fine pitch) (14 ×...
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Page 835 Appendix A Instruction Set List A.1 Convention (a) Register symbols used to describe operands Register Symbol Explanation reg1 General registers: Used as source registers General registers: Used mainly as destination registers. Also used as reg2 source register in some instructions. General registers: Used mainly to store the remainders of division reg3 results and the higher order 3 bits of multiplication results.
Page 836 Appendix A Instruction Set List (c) Register symbols used in operation Register Symbol Explanation ← Input for GR [ ] General register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 837 Appendix A Instruction Set List (e) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (f) Condition codes Condition Condition Code Name Condition Formula Explanation (cccc)
Page 838 Appendix A Instruction Set List A.2 Instruction Set (In Alphabetical Order) (1/4) Execution Flags Clock Mnemonic Operand Opcode Operation CY OV S Z SAT × × × × reg1,reg2 rrrrr001110RRRRR GR[reg2]←GR[reg2] + GR[reg1] × × × × imm5,reg2 rrrrr010010iiiii GR[reg2]←GR[reg2] + sign-extend(imm5) rrrrr110000RRRRR ×...
Page 839 Appendix A Instruction Set List (2/4) Execution Flags Clock Mnemonic Operand Opcode Operation CY OV S Z SAT 0000011110dddddd disp22 ddddddddddddddd0 PC←PC + sign-extend(disp22) Note 7 adr←GR[reg1] + sign-extend(disp16) Note rrrrr111000RRRRR LD.B disp16[reg1],reg2 GR[reg2]←sign-extend(Load-memory(adr,Byte)) dddddddddddddddd rrrrr11110bRRRRR adr←GR[reg1] + sign-extend(disp16) Note LD.BU disp16[reg1],reg2 dddddddddddddd1...
Page 840 Appendix A Instruction Set List (3/4) Execution Flags Clock Mnemonic Operand Opcode Operation CY OV S Z SAT if PSW.EP=1 then PC ←EIPC PSW ←EIPSW else if PSW.NP=1 0000011111100000 RETI then PC ←FEPC 0000000101000000 PSW ←FEPSW else PC←EIPC PSW ←EIPSW GR[reg2]←GR[reg2] arithmetically shift right rrrrr111111RRRRR ×...
Page 841 Appendix A Instruction Set List (4/4) Execution Flags Clock Mnemonic Operand Opcode Operation CY OV S Z SAT adr←(PC+2) + (GR [reg1] logically shift left by 1) PC←(PC+2) + (sign-extend SWITCH reg1 00000000010RRRRR (Load-memory (adr,Half-word))) logically shift left by 1 GR[reg1]←sign-extend reg1 00000000101RRRRR...
Page 842 Appendix A Instruction Set List 16. ff = 00: Load sp in ep. 10: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18.
Page 843 Appendix B Index A/D conversion result register n ........... . . 371 A/D converter mode register 0H .
Page 844 Appendix B Index CSIC1 ............... . 468 CSIL0 .
Page 845 Appendix B Index Main peripheral clock control register ..........235 MPCCTL .
Page 846 Appendix B Index SAR ................369 SELCNT1 .
Page 847 Appendix B Index UAnCTL0 ..............407 UAnCTL1 .
Page 848 User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 849 Appendix C Revision History The following shows the revision history up to present. Application portions signifies the chapter of each edition. (1/2) Edition No. Major items revised Revised Sections Figure 15-6 “DMA Transfer Count Register (DMBCn) Format”, Note, EE3V2 15.3 (5), p.510 bit ACF changed to bit EN Figure 15-10 “Maskable Interrupt Status Flag Format”, bit ACF description 15.3 (7), p.514-516...
Page 850 Appendix C Revision History (2/2) Edition No. Major items revised Revised Sections User’s Manual U16702EE3V2UD00 Downloaded from Elcodis.com electronic components distributor...
Page 851 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.
Page 852 Downloaded from Elcodis.com electronic components distributor...

NEC V850E/RS1 User Manual

Table of Contents

List of Tables

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 CPU Function

Chapter 4 Port Functions

Chapter 5 Bus Control Function

Chapter 6 Clock Generator

Chapter 7 16-Bit Timer/Event Counter P

Chapter 8 16-Bit Timer/Event Counter Q

Chapter 9 16-Bit Interval Timer M

Chapter 10 Functions of Watchdog Timer 2

Chapter 11 A/D Converter

Chapter 12 Asynchronous Serial Interface a (UARTA)

Chapter 13 3-Wire Serial Interface (CSIB)

Chapter 14 Queued CSI (CSI30, CSI31)

Chapter 15 DMA Functions (DMA Controller)

Chapter 16 FCAN Controller

Chapter 17 Interrupt/Exception Processing Function

Chapter 18 Standby Function

Chapter 19 RESET Function

Chapter 20 Regulator

Chapter 21 Flash Memory

Chapter 22 On-Chip Debug Function

Chapter 23 Power-On-Clear Circuit

Chapter 24 Low-Voltage Detector

Chapter 25 Clock Monitor

Chapter 26 CRC Function

Chapter 27 Electrical Specification

Chapter 28 Package Drawing

Chapter 29 Recommended Soldering Conditions

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Summary of Contents for NEC V850E/RS1