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1.6.2 Internal units
(1) CPU
The CPU uses 5-stage pipeline control to execute address calculation, arithmetic and logical operation, data
transfer, and most other instruction processing in one clock.
A multiplier (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits), barrel shifter (32-bit), and other
dedicated hardware are on-chip to accelerate complex instruction processing.
(2) Bus control unit (BCU)
The BCU starts a required external bus cycle based on a physical address obtained from the CPU. If there is
no bus cycle start request from the CPU when fetching an instruction from an external memory area, the BCU
generates a prefetch address and prefetches the instruction code. The prefetched instruction code is fetched
into the internal instruction queue of the CPU.
(3) Memory controller (MEMC)
The MEMC controls SRAM, ROM, and various I/O for external memory expansion.
(4) DMA controller (DMAC)
The DMA transfers data between memory and I/O in place of the CPU.
The address mode is two-cycle transfer. The three bus modes are single transfer, single-step transfer, and
block transfer.
(5) ROM
There is on-chip flash memory (256 KB) in the µ PD70F3116, and mask ROM (256 KB) in the µ PD703116.
On an instruction fetch, the ROM can be accessed by the CPU in one clock.
When single-chip mode 0 or flash memory programming mode is set, ROM is mapped starting from address
00000000H.
When single-chip mode 1 is set, it is mapped starting from address 00100000H.
ROM cannot be accessed if ROMless mode 0 or 1 is set.
(6) RAM
RAM is mapped starting from address FFFFC000H.
It can be accessed by the CPU in one clock on an instruction fetch or data access.
(7) Interrupt controller (INTC)
The INTC services hardware interrupt requests from on-chip peripheral I/O and external sources (NMI, INTP0
to INTP6, INTP20 to INTP25, INTP30, INTP31, INTP100, INTP101, INTP110, INTP111). For these interrupt
requests, eight levels of interrupt priority can be defined and multiprocessing controls against the interrupt
sources can be performed.
(8) Clock generator (CG)
The CG provides a frequency that is 1, 2.5, 5, or 10 times (using the on-chip PLL) or 1/2 times (not using the
on-chip PLL) the input clock (f
resonator to pins X1 and X2 (only when using the on-chip PLL synthesizer) or input an external clock from the
X1 pin.
38
CHAPTER 1 INTRODUCTION
) as the internal system clock (f
X
User's Manual U14492EJ3V0UD
). As the input clock, connect an external
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