Interrupt Control Register (Xxicn) - NEC V850ES/SA2 UPD703201 Manual

14.3.4 Interrupt control register (xxICn)

An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control
conditions for each maskable interrupt request.
This register can be read or written in 8-bit or 1-bit units.
After reset:
xxICn
xxMKn
xxPRn2
Note The flag xxlFn is reset automatically by the hardware if an interrupt request is acknowledged.
Remark xx: Identification name of each peripheral unit (OV, P00 to P03, P10 to P13, CM, DMA, CSI, SE, SR,
ST, AD)
n: Peripheral unit number (None or 0 to 3).
The addresses and bits of the interrupt control registers are as follows.
434
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
47H R/W Address: FFFFF110H to FFFFF15AH
<7> <6>
xxIFn xxMKn 0
xxIFn
0 Interrupt request not issued
1
Interrupt request issued
0 Interrupt servicing enabled
1
Interrupt servicing disabled (pending)
xxPRn1 xxPRn0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Preliminary User's Manual U15905EJ1V0UD
0 0 xxPRn2
Note
Interrupt request flag
Interrupt mask flag
Interrupt priority specification bit
Specifies level 0 (highest).
Specifies level 1.
Specifies level 2.
Specifies level 3.
Specifies level 4.
Specifies level 5.
Specifies level 6.
Specifies level 7 (lowest).
xxPRn1 xxPRn0