Restore - NEC V850ES/SA2 UPD703201 Manual

14.2.2 Restore

(1) From NMI
Execution is restored from the NMI by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
<1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is
0 and the NP bit of the PSW is 1.
<2> Transfers control back to the address of the restored PC and PSW.
Figure 14-3 illustrates how the RETI instruction is processed.
1
Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during non-
maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by
the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the
LDSR instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
(2) From INTWDT
Execution cannot be returned from INTWDT by the RETI instruction. Execute a system reset after the interrupt
has been serviced.
424
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 14-3. RETI Instruction Processing
RETI instruction
PSW.EP
0
PSW.NP
0
PC EIPC
PSW EIPSW
Original processing restored
Preliminary User's Manual U15905EJ1V0UD
1
PC FEPC
PSW FEPSW