Control Registers - NEC V850E/RS1 User Manual

6.3 Control Registers

(1) Main peripheral clock control register (MPCCTL)
This is an 8-bit register that selects the internal clock. This register can be read or written in 8-bit
or 1-bit units.
Data can be written to this register only in combination of specific sequences (refer to 3.2.3
ously both PLL or to use only one PLL. Both PLLs can be assigned respectively to the CPU or to
the peripherals.
Symbol
MPCCTL SELPLL
R/W
SELPLL
Caution:
MCKSEL
Caution:
PCKSEL
Caution:
STPPLL1
Cautions: 1. If this bit is set to "1", it is impossible to set to "0" by register writing. Only
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"Special registers" on page 70). The clock generator flexibility allows to use either simultane-
Figure 6-2: Main Peripheral Clock Control Register (MPCCTL) Format (1/2)
7 6 5
0 0
R/W R R
Main-OSC clock (f = f
0
XX
PLL clock (f = f
1
XX PLL_MCKSEL_CKDIV
When using an 8-bit manipulation instruction, do not change the SELPLL bit with
other bit.
Main clock (f
0
PLL_MCKSEL)
Main clock (f
1
PLL_MCKSEL)
When using PLL clock for CPU, do not change the MCKSEL bit value.
0 Peripheral clock = PLL0 (Default)
1 Peripheral clock = PLL1
When EXCKSEL register value is 01h to 3Fh, do not change PCKSEL bit value.
f clock is provided only to aFCANn, CSI3n and CSIBn (n = 0,1).
PLL_PCKSEL
0 PLL1 executable (Default)
1 PLL1 stop
RESET input can be set to "0".
2. When using PLL1 clock for peripheral functions, do not set to 1 this bit.
User's Manual U16702EE3V2UD00
Chapter 6 Clock Generator
4 3 2
0 MCKSEL PCKSEL STPPLL1 STPPLL0 FFFFF82BH
R R/W R/W
f clock select
XX
)
X
)
Master clock selection register (f
= PLL0 (Default)
= PLL1
Peripheral clock selection register (f
PLL 1 execution stop register
1 0 Address
R/W R/W
)
PLL_MCKSEL
)
PLL_PCKSEL
After reset
80H
235