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14.3.3 Priorities of maskable interrupts
The V850ES/SA2 and V850ES/SA3 provide multiple interrupt servicing in which an interrupt is acknowledged while
another interrupt is being serviced. Multiple interrupts can be controlled by priority levels.
There are two types of priority level control: control based on the default priority levels, and control based on the
programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt
control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are
generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt
request type (default priority level) beforehand. For more information, refer to Table 14-1 Interrupt/Exception
Source List. The programmable priority control customizes interrupt requests into eight levels by setting the priority
level specification flag.
Note that when an interrupt request is acknowledged, the ID flag of PSW is automatically set to 1. Therefore, when
multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in the
interrupt service program) to set the interrupt enable mode.
Remark xx: Identification name of each peripheral unit (AD, BRG, CC, CSI, DMA, IIC, OVF, P, ROV, RTC,
SRE, ST, TM, WDT)
n: Peripheral unit number (None or 0 to 3).
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CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Preliminary User's Manual U15905EJ1V0UD
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