Figure 4-12 Waveform Of A Single Flp; Figure 4-13 Consecutive Flp And Nlp Bursts - Huawei OptiX OSN 550 Configuration Manual

4 Configuring Ethernet Services
NOTE
This topic considers FE electrical interfaces as an example to describe how to implement the auto-negotiation
function.
The FLP is called the 100BASE-T link integrity test pulse sequence. Each set of equipment on
the network must be capable of issuing FLP bursts in the case of power-on, issuing of
management commands, or user interaction. The FLP burst consists of a series of link integrity
test pulses that form an alternating clock/data sequence. Extraction of the data bits from the FLP
burst yields a link code word that identifies the working modes supported by the remote
equipment and certain information used for the negotiation and handshake mechanism.
To maintain interoperability with the existing 100BASE-T equipment, the auto-negotiation
function also supports the reception of 100BASE-T compliant link integrity test pulses. The
10BASE-T link pulse activity is referred to as the NLP sequence. equipment that fails to respond
to the FLP burst sequence by returning only the NLP sequence is treated as the 100BASE-T
compatible equipment.
The first pulse in an FLP burst is defined as a clock pulse. Clock pulses within an FLP burst
occur at intervals of 125 us. Data pulses occur in the middle of two adjacent clock pulses. The
positive pulse represents logic "1" and the absence of a pulse represents logic "0". An FLP burst
consists of 17 clock pulses and 16 data pulses (if all data bits are 1). The NLP waveform is
simpler than the FLP waveform. NLP sends a positive pulse every 16 ms when no data frame
needs to be transmitted.

Figure 4-12 Waveform of a single FLP

First bit on wire

Figure 4-13 Consecutive FLP and NLP bursts

4-12
Data 1
D
Encoding
0
T1: 100 ns
FLP bursts
NLPs
T4: 2 ms
Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
OptiX OSN 550 Multi-Service CPE Optical Transmission
Clock pulses
1 0
D D
1 2
T2: 62.5 us
T5
T4
Configuration Guide
T1
T3
T2
...
1
...
D
...
3
T3: 125 us
T5: 16 ms
Issue 02 (2011-06-30)
System