Data Flow - Xilinx KCU105 User Manual

A lightweight PicoBlaze™ controller is used to set up the SYSMON registers in continuous
sequence mode and read various rail data periodically. The output from the PicoBlaze
controller is made available in block RAM, and an FSM reads various rails from the block
RAM (as shown in
accessed over PCIe through a BAR-mapped region.
The AXI4-Lite IP interface (IPIF) core is used in the design and the interface logic between
the block RAM and the AXI4-Lite IPIF reads the power and temperature monitor registers
from block RAM. Providing an AXI4-Lite slave interface adds the flexibility of using the
module in other designs.
X-Ref Target - Figure 5-10
See the UltraScale Architecture System Monitor User Guide (UG580)
information.

Data Flow

The data transfer between the host and the card uses the following data flow.
S2C Traffic Flow
1. The Host maintains SRC-Q, STAS-Q.
2. Hardware SGL block provides DST-Q through hardware SGL interface.
3. DMA fetches SRC-Q and buffer pointed to by SRC-Q.
4. DMA provides data on AXI MM interface as indicated by the DST-Q SGL element.
5. Due to use of a hardware SGL interface, DMA does not fetch DST-Q elements and there
is no STAD SGL involved.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure 5-10) and updates the user space registers. These registers can be
Figure 5-10: PVTMON Functional Block Diagram
www.xilinx.com
[Ref 9] for more
54
Send Feedback