Xilinx KCU105 User Manual page 58

Figure 5-11 provides a functional block diagram of the SGL model of operation used in the
TRD.
X-Ref Target - Figure 5-11
Channel 0 SW
Descriptor
Host SGL
I/O Buffer
I/O Buffer
I/O Buffer
Host SGL
(Channel 0)
Expresso DMA Aware
Hardware Logic
• Descriptors: There are four SGL descriptors instantiated (assuming all four channels
are in use). One SGL descriptor has to be created for each channel (host SGL) to use.
The XDMA driver creates an SGL corresponding to each SGL descriptor. The application
driver passes a pointer to the SGL descriptor to APIs when it wants to perform any
operation on the SGL, for example, perform I/O, activate SGL, stop I/O, and so on after
the creation of the SGL descriptor.
• Host SGL: There is one host SGL per channel and it is used by the application driver by
invoking APIs to perform operations on the SGL, for example, to perform I/O, activate
SGL, stop I/O, and so on. The host SGL list elements are used to point to I/O buffers
which are source or sink (destination) of data, depending on the direction in which the
channel is used for data transfer. In the S2C direction, host SGL elements point to
source I/O buffers and in the C2S direction. the host SGL elements point to sink
(destination) I/O buffers. The I/O buffers belong to (that is, are resident on) the host.
An important attribute of host SGL loc_axi is set to false to indicate to Expresso DMA
that the I/O buffer being pointed to by the SGL element is present on the host.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Channel 1 SW Channel 2 SW
Descriptor
Host SGL
I/O Buffer
I/O Buffer
I/O Buffer
Host SGL
(Channel 1)
Populate
Buffer
Descriptors
(BDs) for I/Os
BD
Figure 5-11: SGL Model of Operation
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Channel 3 SW
Descriptor
Host SGL
I/O Buffer
I/O Buffer
I/O Buffer
Host SGL
(Channel 2)
Buffer Descriptor
BD BD
(BD) FIFO
Host Memory
Descriptor
Host SGL
I/O Buffer
I/O Buffer
I/O Buffer
Host SGL
(Channel 3)
PCIe Link
Endpoint Memory
I/O Buffer
I/O Buffer
I/O Buffer
PCIe Endpoint
UG920_c5_11_111114
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