Xilinx KCU105 User Manual page 44

These queues can be resident either in host memory or can be provided by the hardware
SGL submission block depending on the channel (S2S/C2S). The software driver sets up the
queue elements in contiguous locations and DMA handles wraparound of the queue. Every
DMA channel has these registers which pertain to each queue:
• Q_PTR: Starting address of the queue
• Q_SIZE: Number of SGL elements in queue
• Q_LIMIT: Index of the first element still owned by the software; DMA hardware wraps
around to start element location when Q_LIMIT is equal to Q_SIZE.
Figure 5-3 depicts DMA operation.
X-Ref Target - Figure 5-3
Using Expresso DMA for Streaming Applications
The Expresso DMA IP core provides an additional interface called Hardware-SGL interface
for FIFO mode applications that require AXI-Stream data transfers. The Hardware-SGL mode
allows hardware logic to manage one set of SGL-Qs per DMA channel.
To summarize the Hardware-SGL operation:
• In the S2C direction, host software manages SRC-Q and STAS-Q elements. DST-Q
elements are provided by hardware logic (through the SGL interface). There is no
STAD-Q involved. The data from DMA is available on the AXI interface with additional
sidebands (which are part of the awuser port) providing information on actual packet
byte count which can be used to build packets across the AXI-Stream interface.
• In the C2S direction, host software manages DST-Q and STAD-Q elements. SRC-Q
elements are provided by the hardware logic (through the SGL interface) based on
incoming data received from the AXI-Stream application. There is no STAS-Q involved.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure 5-3: DMA Operation
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