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Xilinx KCU105 User Manual

Xilinx KCU105 User Manual

10gbase-r ethernet trd
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KCU105 10GBASE-R
Ethernet TRD User Guide
KUCon-TRD04
Vivado Design Suite
UG921 (v2016.3) October 25, 2016

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Summary of Contents for Xilinx KCU105

  • Page 1 KCU105 10GBASE-R Ethernet TRD User Guide KUCon-TRD04 Vivado Design Suite UG921 (v2016.3) October 25, 2016...

  • Page 2: Revision History

    Updated all references to Vivado Design Suite version 2015.1 to 2015.2. Updated all references to Vivado Design Suite version 2014.4.1 to 2015.1. 04/27/2015 2015.1 02/25/2015 2014.4.1 Initial Xilinx Release. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 3: Table Of Contents

    Program the KCU105 Evaluation Board ........
  • Page 4 Xilinx Resources ........

  • Page 5: Chapter 1: Introduction

    10GBASE-R TRD Overview The 10GBASE-R TRD targets the Kintex® UltraScale™ XCKU040-2FFVA1156E FPGA running on the KCU105 evaluation board. It demonstrates 10-Gigabit Ethernet connectivity using 10-Gigabit Ethernet PCS/PMA IP (10GBASE-R) and 10-Gigabit Ethernet MAC IP (10G MAC) cores on two channels. The data source for these channels can be configured to be either from an internal or external Traffic Generator.
  • Page 6 A MicroBlaze™ processor-based subsystem monitors the 10-Gigabit Ethernet MAC IP core statistics and passes the information to the Ethernet Controller application (GUI) running on the control computer using the USB-to-UART port on the KCU105 board. This subsystem also controls the Traffic Generator and monitors Ethernet performance.
  • Page 7 Provides the controller interface for asynchronous serial data transfer. This interface ° connects to the USB-to-UART port on the KCU105 board, and is used to communicate with the control computer. Provides an AXI4-Lite interface on the other end to communicate with the °...
  • Page 8 Chapter 1: Introduction Table 1-1: 10GBASE-R TRD Resource Utilization (Cont’d) Resource Type Used Available Usage (%) GTHE3_COMMON 20.00 SYSMONE1 100.00 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 9: Chapter 2: Setup

    Setup This chapter lists the requirements and describes how to do all preliminary setup of the KCU105 board, control computer, and software before bringing up the 10GBASE-R TRD. Perform the procedures described in this chapter before performing the bring up...

  • Page 10: Preliminary Setup

    Guide (UG1033)[Ref Configure the Control Computer COM Port The 10GBASE-R TRD uses the Ethernet Controller application to communicate between the control computer and the KCU105 board. To configure the control computer COM ports for this purpose: 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 11 Figure 2-1. X-Ref Target - Figure 2-1 Figure 2-1: Connection Diagram for Preliminary Setup 2. Power on the KCU105 board by placing switch SW1 to the ON position (SW1 in Figure 2-1). 3. Open the control computer Device Manager (Figure 2-2).
  • Page 12 Installation of Java 1.7 is required for the Ethernet Controller Application. Download Java SE Runtime Environment 7 from Oracle and install it on the control computer. Follow the installation instructions provided with the software. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 13 Figure 2-4: Directory Location, Ethernet Controller Installer 2. Right-click either the EthernetController-32-installer (for a 32-bit operating system) or EthernetController-64-installer (for a 64-bit operating system) and click Run as administrator (Figure 2-4). 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 14 5. Browse to the location where the Ethernet Controller application will be installed and click Install (Figure 2-6). X-Ref Target - Figure 2-6 Figure 2-6: Ethernet Controller Installation Location 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 15 To uninstall the Ethernet Controller application after design bring up, open the Control Panel. In TIP: the Control Panel, click All Control Panel Items>Programs and Features and uninstall program “Xilinx Ethernet Controller - Powered by Xilinx.” Ready to Bring Up the Design After all procedures in this chapter are complete, go to Chapter 3, Bringing Up the Design.

  • Page 16: Chapter 3: Bringing Up The Design

    1. Connect the KCU105 board to the control computer and power supply as shown in Figure 3-1. 2. Insert the SFP+ modules into the SFP cage on the KCU105 board and the connect the fiber optic cables (also shown in Figure 3-1).
  • Page 17 Chapter 3: Bringing Up the Design 4. Power on the KCU105 board by placing switch SW1 to the ON position (SW1 in Figure 3-1). 5. Launch the Vivado Integrated Design Environment (IDE) on the control computer: a. Select Start > All Programs > Xilinx Design Tools > Vivado 2016.3 > Vivado 2016.3.
  • Page 18 Chapter 3: Bringing Up the Design 6. Open the connection wizard to initiate a connection to the KCU105 board: a. Click Open a new hardware target (Figure 3-3). X-Ref Target - Figure 3-3 Figure 3-3: Using the User Assistance Bar to Open a Hardware Target 10GBASE-R Ethernet TRD www.xilinx.com...
  • Page 19 Chapter 3: Bringing Up the Design b. Configure the wizard to establish connection with the KCU105 board by selecting the default value on each wizard page. Click Next > Next > Next > Finish. c. In the hardware view, right-click xcku040 and click Program Device (Figure 3-4).
  • Page 20 In the Bitstream file field, browse to the location of the BIT file: <working_dir>/kcu105_10gbaser_trd/ready_to_test/kcu105_10gbase r_download.bit and click Program (Figure 3-5). X-Ref Target - Figure 3-5 Figure 3-5: Program Device Window After completing these steps, continue on to Running the Design. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 21: Running The Design

    Bringing Up the Design Running the Design Launch the Ethernet Controller Application 1. Launch the Ethernet Controller application on the control computer. In Windows, click Start > All Programs > Xilinx > EthernetController (Figure 3-6). X-Ref Target - Figure 3-6...
  • Page 22 The COM port associated with the Silicon Labs CP210x USB to UART Bridge can be identified using TIP: the Windows Device Manager. See step 3, page X-Ref Target - Figure 3-7 Figure 3-7: Select COM Port Associated with the USB to UART Bridge 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 23 Internal Generator and enter 1500 in the payload field, and click Start for both channels. X-Ref Target - Figure 3-8 Figure 3-8: Set Payload Size on Channel 0 and Channel 1 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 24 The relationship between payload size and throughput can be demonstrated by changing the TIP: payload size. Reducing the payload size causes a dip in performance. Refer to Appendix B, Performance Estimates for performance estimation on 10G Ethernet protocol. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 25 Appendix D, Testing with an External Traffic Generator describes how to setup and test the TIP: 10GBASE-R TRD using an external Ixia NGY-NP4-01 10 Gigabit Application Network Processor Load Module. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 26 Bringing Up the Design 5. Select the Power Plot tab to view the FPGA power consumption and die temperature (Figure 3-11). X-Ref Target - Figure 3-11 Figure 3-11: Power Plots 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 27: Chapter 4: Implementing And Simulating The Design

    1. Launch the Vivado Integrated Design Environment (IDE) on the control computer and set up the reference design project. • On Windows 7: a. Click Start > All Programs > Xilinx Design Tools > Vivado 2016.3 > Vivado 2016.3. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 28 On a terminal window, change directory to <working_dir>/kcu105_10gbaser_trd/hardware/vivado b. At the command prompt enter: vivado -source scripts/kcu105_10GBASER_trd.tcl The Vivado IDE will display the 10gbaser_trd project populated with sources (Figure 4-2). 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 29 When building the design on Windows, if this error occurs: Path Length Exceeds IMPORTANT: 260-Bytes maximum allowed by Windows, move the kcu105_10gbaser_trd directory directly under C:\. X-Ref Target - Figure 4-2 Figure 4-2: 10gbaser_trd Vivado project 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 30 Figure 4-3: Vivado Project, Sources View 3. In the Flow Navigator, click Generate Bitstream. 4. In the No Implementation Results Available window, click Yes. The bitstream will be generated and available at: <working_dir>/kcu105_10gbaser_trd/hardware/vivado/runs/impl_run/ 10gbaser_trd.runs/impl_1/kcu105_10gbaser_top.bit 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 31 The IPI Block Design, mac_phy.bd must be open to successfully export the design to the IMPORTANT: SDK. X-Ref Target - Figure 4-4 Figure 4-4: Export Hardware to the SDK from Vivado 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 32 3. To launch SDK from the Vivado IDE menu bar, select File > Launch SDK. In the launch SDK window click OK, SDK window will open with the hardware platform populated (Figure 4-6). X-Ref Target - Figure 4-6 Figure 4-6: Launch SDK 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 33 4. In the SDK window (Figure 4-7) select File > New > Application Project to build an application. X-Ref Target - Figure 4-7 Figure 4-7: Creating an Application Project in the SDK 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 34 Chapter 4: Implementing and Simulating the Design 5. In the Application Project window (Figure 4-8) enter the project name as kcu105_10gbaser_top and click Next. X-Ref Target - Figure 4-8 Figure 4-8: Assign Project Name 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 35 Chapter 4: Implementing and Simulating the Design 6. Select Empty Application and click Finish (Figure 4-9). X-Ref Target - Figure 4-9 Figure 4-9: Select Empty Application 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 36 7. In the project explorer tab (Figure 4-10), right-click kcu105_10gbaser_top, select Import, and under the General tab select File System. Click Next. X-Ref Target - Figure 4-10 Figure 4-10: Importing File System 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 37 Select the source directory in the left pane and click Finish (Figure 4-11). The application ELF file will be generated and available at: <working_dir>/kcu105_10gbaser_trd/hardware/vivado/runs/impl_run/10gb aser_trd.sdk/kcu105_10gbaser_top/Debug/kcu105_10gbaser_top.elf X-Ref Target - Figure 4-11 Figure 4-11: Importing software/source Directory 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 38 X-Ref Target - Figure 4-12 Figure 4-12: Run Script to Create download.bit The create_download_bit.tcl script runs the update_mem command and combines kcu105_10gbaser_top.bit and kcu105_10gbaser_top.elf into single bitfile available at: <working_dir>/kcu105_10gbaser_trd/hardware/vivado/runs/impl_run/10g baser_trd.runs/impl_1/kcu105_10gbaser_download.bit 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 39: Simulating The Design

    The testbench for the 10GBASE-R TRD is available at: <working_dir>/kcu105_10gbaser_trd/hardware/sources/testbench/tb.v. Before running a simulation the 10gbaser_trd project must be open and step 1 under IMPORTANT: Generate the Hardware Bitstream should have been executed. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 40 To run simulation in Modelsim/Questa: 1. In the flow navigator panel, under Simulation, click Run Simulation > Run Behavioral Simulation (Figure 4-13). X-Ref Target - Figure 4-13 Figure 4-13: Run Modelsim Simulation 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 41 3. In the Flow Navigator Panel, under Simulation, click Simulation > Run behavioral simulation. When simulating the design on Windows, use this command to prevent the path length IMPORTANT: from exceeding 260 bytes: exec subst A:<working dir>\rdf0308-kcu105-trd04-2016-1\kcu105_10gbaser_trd\hardware 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 42: Chapter 5: Reference Design Details

    This chapter describes the hardware design and software components. Hardware Figure 5-1 shows a block-level overview of the 10GBASE-R TRD. X-Ref Target - Figure 5-1 Figure 5-1: 10GBASE-R TRD Block Diagram 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 43 5]) using the SFI electrical specification. The SFP+ optical transceiver module plugs into an SFP cage on the KCU105 evaluation board. The external Traffic Generator communicates with this IP via the SFP+ interface. More information is available at the 10 Gigabit Ethernet PCS/PMA (10GBASE-R) website...
  • Page 44 Internal Traffic Generator, Generator Module The Generator module generates Ethernet packets based on user inputs provided from the Ethernet Controller application running on the control computer. Data payload size can be 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 45 When tx_axis_tlast is not asserted, the only valid value is 0xFF. When tx_axis_tlast is asserted, valid values are 0x01 to 0xFF. End of frame indicator on transmit packets. Valid only along with assertion tx_axis_tlast Output of tx_axis_tvalid. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 46 10-Gigabit Ethernet MAC IP core. The source and destination MAC addresses are parameters into the loopback module. Table 5-3 shows the parameters and ports on the loopback module. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 47 Source ready to provide data. Indicates that the MAC is presenting valid data on rx_axis_tdata. rx_axis_tvalid Input rx_axis_tuser input if asserted indicates a good packet is received. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 48 Traffic Generator block and the 10G MAC. At the end of the packet (tx_tlast) 14 bytes of header are subtracted from the count to get payload count. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 49 MAC IP core is ready to accept data on tx_axis_tdata. tx_axis_tready Input The simultaneous assertion of tx_axis_tvalid and tx_axis_tready marks the successful transfer of one data beat on tx_axis_tdata. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 50 To reuse this block, the control and status signals into the register map must be changed. Appendix C, User-Space Registers describes the registers implemented in the Traffic Generator and Monitor block. Figure 5-3 shows the user register interface. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 51 The Ethernet Controller application running on the control computer sends control information and receives status to and from different components of the 10GBASE-R TRD using the MicroBlaze processor subsystem. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 52 AXI UART Lite which communicates with the Ethernet Controller application running on the control computer • System Management wizard for SYSMON • Channel 0, the 10-Gigabit Ethernet MAC IP core 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 53 For more details on AXI UART Lite, see AXI UART Lite LogiCORE IP Product Guide (PG142) [Ref 15] and the AXI UART Lite website [Ref 16]. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 54 An external reset (a debounced pushbutton switch) drives the 10-Gigabit Ethernet PCS/PMA IP cores, the 10-Gigabit Ethernet MAC IP cores and the Processor Subsystem Reset IP core in the MicroBlaze processor System after being debounced. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 55 X-Ref Target - Figure 5-8 Figure 5-8: Resets For details on the Processor System Reset Module, see the Processor System Reset Module website [Ref 17]. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 56: Software

    Throughput numbers and graphs when a test is executing • 10-Gigabit Ethernet MAC IP statistics • Power consumption and temperature for the FPGA device • Block diagram of the design 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 57 Payload size: Specify the size of packets when running in internal generator mode. The GUI interacts with the KCU105 board through the UART COM port exposed by the Silicon Labs UART driver. All transmitted and received data adheres to a custom command model followed by the client and server.
  • Page 58 An example Read command output response : F000000F. Write Command W <Command Number denoted as a 4-character hexadecimal numeric string AAAA> < Data, represented as an 8-character hexadecimal numeric string DDDDDDDD> 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 59 The software Figure 5-11. layers are as shown in X-Ref Target - Figure 5-11 Figure 5-11: Software Layers in the MicroBlaze Processor Server Application 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 60 7. The Command Interpreter functionality is different for Single Read and Bulk Read commands. 8. For a single read request, command number shall give the index of the integer array where the referenced register offset is placed. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 61 The source code for the MicroBlaze application is available under the software/source directory (see Appendix A, Directory Structure). The command mapping is defined in CommandDesc.h in the source directory. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 62: Appendix A: Directory Structure

    The files and folders contained in the 10GBASE-R TRD are described here. The top-level folder is kcu105_10gbaser_trd. hardware Folder The hardware folder contains all the required sources needed to generate a bitstream. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 63 The runs folder is created when the Tcl script file is sourced. The runs folder contains the output of simulation, synthesis and implementation processes. ready_to_test Folder The ready_to_test folder contains the bit file to program the KCU105 evaluation board. software Folder The software folder contains the software design deliverables.
  • Page 64 Payload size/Packet size * 100 (Gb/s) 64/(38 + 64) = 62.7% 6.27 512/(38 + 512) = 93.1% 9.31 1024 1024/(38 + 1024) = 96.3% 9.63 1500 1500/(38 + 1500) = 97.5% 9.75 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 65: Appendix C: User-Space Registers

    Software version: Indicates the Vivado® Design Suite version 15:4 Read Only used when developing this reference design. For example, 12’h141 Vivado Design Suite 2014.1 is indicated by 141. 31:16 Target Board: KCU105 board. 16’h0105 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 66 Enable loopback if external generator is selected. Enable generator if internal generator is selected. Read or Write Ethernet frame data payload size. Allowed values (46 bytes to 31:16 d'125 1,500 Bytes). 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 67 Design was developed in which Vivado version 141 = Vivado 14:5 Read Only 12’h141 Design Suite 14.1 31:16 Target Board. KCU105 board. 16’h0105 Table C-9: Ethernet Performance Monitor, Transmit Payload Byte Count Register (0x4AA1_0004) Bit Position Mode Default Value Description Sample count.
  • Page 68 Table C-14: Loopback module and PHY status Register (0x4AA1_00x18) Bit Position Mode Default Value Description PHY is up. Read Only Packets dropped in loopback mode when external traffic generator is selected. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 69: Appendix D: Testing With An External Traffic Generator

    Appendix D Testing with an External Traffic Generator This appendix describes how to setup and test the 10GBASE-R TRD running on the KCU105 board using an Ixia NGY-NP4-01 10 Gigabit Application Network Processor Load Module (Ixia load module). Requirements Hardware •...

  • Page 70: Program The Kcu105 Evaluation Board

    IxExplorer (The IXIA controller application) Program the KCU105 Evaluation Board This section describes how to setup the KCU105 board with the Ixia load module and control computer and how to program the FPGA with the 10GBASE-R TRD BIT file.
  • Page 71 X-Ref Target - Figure D-1 Figure D-1: KCU105 Board and Ixia Module Connections Port 1 of the Ixia load module is connected to connector SPF 1 on the KCU105 board IMPORTANT: which is Channel 1 in the reference design. Port 2 of the Ixia tester is connected to connector SPF 0 on the KCU105 board which is Channel 0 in the reference design.
  • Page 72 Appendix D: Testing with an External Traffic Generator 3. Launch the Vivado Integrated Design Environment (IDE) on the control computer: a. Select Start > All Programs > Xilinx Design Tools > Vivado 2016.3 > Vivado 2016.3. b. On the getting started page, click Open Hardware Manager (Figure D-2).
  • Page 73 Figure D-3: Using the User Assistance Bar to Open a Hardware Target b. Configure the wizard to establish connection with the KCU105 board by selecting the default value on each wizard page. Click Next > Next > Next > Next > Finish.
  • Page 74 Appendix D: Testing with an External Traffic Generator c. In the hardware view, right-click on xcku040 and click program device... (Figure D-4). X-Ref Target - Figure D-4 Figure D-4: Select Device to Program 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 75 Program (Figure D-5). X-Ref Target - Figure D-5 Figure D-5: Program Device Window After completing these steps, continue on to Set Up the Ixia Load Module Parameters. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 76: Set Up The Ixia Load Module Parameters

    2. Launch Ixia IxExplorer on the Ixia chassis. Click Start > All Programs > Ixia > Ixia Application Selector > IxOS > IxOS 6.10.750.5 EA > Ixia IxExplorer (Figure D-6). X-Ref Target - Figure D-6 Figure D-6: Open Ixia IxExplorer 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 77 Appendix D: Testing with an External Traffic Generator 3. Confirm the link between the KCU105 board and the Ixia load module is up. The green icons shown Figure D-7 shows that Port 01 and Port 02 are connected and operating.
  • Page 78 4. Click the + next to Port 01 and Port 02 to expand both ports (Figure D-8). X-Ref Target - Figure D-8 Figure D-8: Expanded Port 01 and Port 02 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 79 Appendix D: Testing with an External Traffic Generator 5. Click Packet Streams on Port 01 to display Ethernet packet parameters (Figure D-9). X-Ref Target - Figure D-9 Figure D-9: Open Packet Streams on Port 01 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 80 Source Address: 00 00 00 44 44 All other parameters should match values and selections shown in Figure D-10. X-Ref Target - Figure D-10 Figure D-10: Set Frame Size and Addresses (DA/SA Tab) 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 81 X-Ref Target - Figure D-11 • • • • • • • • • • • • • • • • • • • Figure D-11: Set Frame Type to 802.3 (Protocols Tab) 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 82 Ixia load module clock source and the KCU105 board clock source. In this lab setup, the Ixia load module clock is running faster than the KCU105 board clock. Because the TRD loops back the data coming from the Ixia load module through a FIFO, this FIFO will overflow at some point of time if the IPG is set to 12 on both the Ixia load module and the 10GBASE-R TRD.

  • Page 83: Running The Design

    Appendix D: Testing with an External Traffic Generator Running the Design Launch the Ethernet Controller Application 1. Launch the Ethernet Controller application on the control computer. Click Start > All Programs > Xilinx > EthernetController (Figure D-13). X-Ref Target - Figure D-13 Figure D-13: Ethernet Controller Application 2.
  • Page 84 3. Ethernet channel 0 and channel 1 are up and ready when the ETH0 PHY and ETH1 PHY indicators are green. For both channels select External Generator and click Start (Figure D-15). X-Ref Target - Figure D-15 Figure D-15: Set External Generator on the Channels 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 85: Start Traffic Generation

    1. To start traffic generation by the Ixia load module, switch to IxExplorer on the Ixia chassis, and right-click on Port 01 Statistics view and click on Start Transmit (Figure D-16). X-Ref Target - Figure D-16 Figure D-16: Start Traffic on Port 01 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 86 X-Ref Target - Figure D-17 • • • • • • • • • • • • • • • • • • • Figure D-17: Start Traffic on Port 02 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 87 Reducing the payload size set in IxExplorer will cause a dip in performance. Refer to Appendix B, Performance Estimates for performance estimation on 10G Ethernet protocol. X-Ref Target - Figure D-18 Figure D-18: Throughput Performance Plots, External Generator 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 88 D-19), stop traffic generation on Port 01 by right-clicking on Port 01 Statistics view then click on Stop Transmit. X-Ref Target - Figure D-19 Figure D-19: Stop Traffic on Port 01 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 89 Appendix D: Testing with an External Traffic Generator 5. Repeat step 4 on Port 02 (Figure D-20). X-Ref Target - Figure D-20 Figure D-20: Stop Traffic on Port 02 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 90 6. Select Statistics View for Port 01 (Figure D-21) and verify if any packets were in error or were dropped. X-Ref Target - Figure D-21 Figure D-21: Traffic Statistics on Port 01 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 91 Port 01. The transmit frame count for Port 01 should match the receive frame count for Port 02. X-Ref Target - Figure D-22 Figure D-22: Traffic Statistics on Port 02 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 92 8. Using the Ethernet Controller application, select the Channel 0 Statistics tab and verify if any packets were in error or were dropped (Figure D-23). X-Ref Target - Figure D-23 Figure D-23: Channel 0 MAC Statistics 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...
  • Page 93 Other IxExplorer traffic options can be used to test the 10GBASE-R Ethernet targeted reference TIP: design. 10GBASE-R Ethernet TRD www.xilinx.com Send Feedback UG921 (v2016.3) October 25, 2016...

  • Page 94: Appendix E: Additional Resources And Legal Notices

    For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. Solution Centers See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips. References...

  • Page 95: Training Resources

    Ixia XM2 Portable Chassis, NGY-NP4-01 10-Gigabit Application Network Processor Load Module and software CD 20. KCU105 Evaluation Board for the Kintex UltraScale FPGA (UG917) Amphenol Corporation Amphenol part number FO-10GGBLCX20-001, LC-LC Duplex 10Gb Multimode 50/125 OM3 Fiber Optic Patch Cable - 2 x LC Male to 2 x LC Male...

  • Page 96: Please Read: Important Legal Notices

    Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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