Ethernet Mac Registers - Xilinx KCU105 User Manual

Table C-6: Sequence End Count Register (0x44A0_0014)
Bit Position Mode
31:0 R/W
Table C-7: Status Register (0x44A0_0018)
Bit Position Mode
31:1 R/W
0 Read only

Ethernet MAC Registers

This section lists register map details for the MAC ID configuration for two MACs and PHY
status.
Table C-8: MAC_0 Promiscuous Mode Enable Register (0x44A0_1400)
Bit Position Mode
31:1 Read only
0 R/W
Table C-9: MAC_0_ID_LOW Register (0x44A0_1404)
Bit Position Mode
31:0 R/W
Table C-10: MAC_0_ID_HIGH Register (0x44A0_1408)
Bit Position Mode
31:16 Read only
15:0 R/W
Table C-11: MAC_1 Promiscuous Mode Enable Register (0x44A0_140C)
Bit Position Mode
31:1 Read only
0 R/W
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Default Value
Wrap count.
0
Value at which the sequence number should wrap around.
Default Value
Reserved
0
Indicates data mismatch in Checker mode.
0
Value of 1 indicates a mismatch in Checker mode.
Default Value
0x0000 Reserved
0x1 MAC_0 Promiscuous mode Enable.
Value of 1 enables Promiscuous mode.
Default Value
Ethernet MAC 0 address lower 32 bits.
0xCCDDEEFF
Default Value
Reserved
0x0000
Ethernet MAC 0 address upper 16 bits.
0xAABB
Default Value
0x0000 Reserved
0x1 MAC_1 Promiscuous mode Enable.
Value of 1 enables Promiscuous mode.
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Appendix C: Register Space
Description
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