Features - Xilinx KCU105 User Manual

Features

The TRD includes these features:
• Hardware
Integrated Endpoint block for PCI Express
°
- 8 lanes, each operating at 5 GT/s (gigatransfers per second) per lane per
direction
- 128-bit at 250 MHz
DMA bridge core
°
- Scatter gather enabled
- 4 channels: 2 channels are used as S2C and 2 as C2S
- Support for an AXI3 interface
- Two ingress and two egress translation regions supported
The IP can support a higher number of translation regions. The netlist used here is
Note:
built to support only two such regions. Contact Northwest Logic for further customization of
[Ref 1]
IP
SGL DMA interface block
°
- Queue management of channels: Destination queue for S2C and source queue
for C2S
- AXI memory map (MM) to AXI-stream interface conversion and AXI-stream to
MM conversion
- 128-bit at 250 MHz rate operation
- SGL submission block interface between the DMA bridge core and the SGL
preparation block for SGL element submission to DMA channels on a
round-robin basis across channels
- Traffic generator (packets on AXI4-stream interface) and checker block
operating at a 128-bit, 250 MHz rate
- AXI performance monitor capturing AXI4-stream interface throughput numbers
- Two 10G Ethernet MAC, PCS PMA blocks operating at 64-bit, 156.25 MHz
• Software
64-bit Linux kernel space drivers for DMA and a raw data driver
°
64-bit Windows 7 drivers for DMA and a raw data driver
°
User space application
°
Control and monitoring graphical user interface (GUI)
°
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
.
www.xilinx.com
Chapter 1: Introduction
7
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