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Xilinx KCU105 User Manual

Pci express control plane trd
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Download this manual See also: User Manual
KCU105 PCI Express
Control Plane TRD
User Guide
KUCon-TRD01
Vivado Design Suite
UG918 (v2017.2) July 18, 2017

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Summary of Contents for Xilinx KCU105

  • Page 1 KCU105 PCI Express Control Plane TRD User Guide KUCon-TRD01 Vivado Design Suite UG918 (v2017.2) July 18, 2017...

  • Page 2: Revision History

    05/05/2015 2015.1 Updated for Vivado Design Suite 2015.1. TRD ZIP file changed to rdf0305-kcu105-trd01-2015-1.zip. Updated Information about resource utilization for the base design and the user extension design in Table 1-1 Table 1-2. Added information about Windows 7 driver support of the reference...
  • Page 3 Reference Design Modifications ........... . . 41 PCI Express Control Plane TRD www.xilinx.com Send Feedback...
  • Page 4 Xilinx Resources ........

  • Page 5: Overview

    Overview The TRD targets the Kintex® UltraScale™ XCKU040-2FFVA1156E FPGA running on the KCU105 evaluation board. It demonstrates a control plane application using a PCI Express Endpoint block in a x1 Gen1 configuration. Simple base address register (BAR)-mapped read and write transactions are demonstrated using a kernel mode software driver controlled by the Control &...

  • Page 6: Features

    Resource Type Available Used Usage (%) CLB registers 484,800 43,896 9.05 CLB LUT 242,400 27,431 11.32 Block RAM 3.66 MMCME3_ADV Global Clock Buffers 1.25 BUFG_GT 4.17 SYSMONE1 3.08 PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 7 Available Used Usage (%) CLB Registers 484,800 44,395 9.16 CLB LUTs 242,400 27,817 11.48 Block RAM MMCME3_ADV Global Clock Buffers 1.25 BUFG_GT 4.17 SYSMONE1 3.08 GTHE3_CHANNEL GTHE3_COMMON PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 8: Requirements

    Requirements Hardware Board and Peripherals • KCU105 board with the Kintex® UltraScale™ XCKU040-2FFVA1156E FPGA • USB cable, standard-A plug to micro-B plug (Digilent cable) • Power supply: 100 VAC–240 VAC input, 12 VDC 5.0A output •...

  • Page 9: Preliminary Setup

    Download the Targeted Reference Design Files 1. Download rdf0305-kcu105-trd01-2017-2.zip from the Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit - Documentation & Designs website. This ZIP file contains the hardware design, software drivers, and application GUI executables. 2. Extract the contents of the file to a working directory.
  • Page 10 Chapter 2: Setup X-Ref Target - Figure 2-1 UG918_c2_01_040315 Figure 2-1: Disable Driver Signature Enforcement PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 11: Install Drivers

    6. After installation is complete, click Finish to exit the InstallShield Wizard. Set DIP Switches Ensure that the DIP switches and jumpers on the KCU105 board are set to the factory default settings as identified in the Kintex UltraScale FPGA KCU105 Evaluation Board User...
  • Page 12 1. Remove all rubber feet and standoffs from the KCU105 board. 2. Power down the host chassis and disconnect the power cord. Remove the power cord to prevent electrical shock or damage to the KCU105 board or other CAUTION! components.
  • Page 13 ATX power supply. X-Ref Target - Figure 2-4 UG918_c3_02_040715 Figure 2-4: Power Supply Connection to the KCU105 Board 7. Slide the KCU105 board power switch SW1 to the ON position (ON/OFF is marked on the board). PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 14: Set The Host System To Boot From The Livedvd (Linux)

    If an external power supply is used instead of the ATX power, the FPGA can be configured Note: first. Then power on the host system. 2. Place the Fedora 20 LiveDVD into the DVD drive. 3. Select the option to boot from DVD. PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 15: Configure The Fpga

    Configure the FPGA While in BIOS, program the FPGA with the BIT file: 1. Connect the standard-A plug to micro-B plug USB cable to the JTAG port on the KCU105 board and to the control computer laptop as shown in Figure 3-1.
  • Page 16 Bringing Up the Design 2. Launch the Vivado® Integrated Design Environment (IDE) on the control computer: a. Select Start > All Programs > Xilinx Design Tools > Vivado 2017.2 > Vivado 2017.2. b. On the getting started page, click Open Hardware Manager (Figure 3-2).
  • Page 17 Chapter 3: Bringing Up the Design 3. Open the connection wizard to initiate a connection to the KCU105 board: a. Click Open New Target (Figure 3-3). X-Ref Target - Figure 3-3 UG918_c3_05_070717 Figure 3-3: Using the User Assistance Bar to Open a Hardware Target PCI Express Control Plane TRD www.xilinx.com...
  • Page 18 Chapter 3: Bringing Up the Design 4. Configure the wizard to establish connection with the KCU105 board by selecting the default value on each wizard page. Click Next > Next > Next > Finish. a. In the hardware view, right-click xcku040 and click Program Device (Figure 3-4).
  • Page 19 UG918_c3_07_070717 Figure 3-5: Program Device Window 5. Check the status of the design by observing the GPIO LEDs positioned at the top right corner of the KCU105 board (Figure 3-6). After FPGA configuration, the LED status from left to right indicate LED position 1: Heartbeat LED, flashes if the PCIe user clock is present °...
  • Page 20 To know that the PCIe Endpoint is discovered, see Check for PCIe Devices, page ° If the PCIe Endpoint is not discovered, reboot the system. Do not power off. ° PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 21: Run The Design On The Host Computer

    $ lspci | grep -i xilinx The following is displayed: 03:00.0 Memory controller: Xilinx Corporation Device 8011 If the host computer does not detect the Xilinx PCIe Endpoint, does not show a Note: lspci Xilinx device.
  • Page 22 Click Install and the drivers are installed. This takes you to the Control and Monitoring GUI as shown in Figure 3-12, page X-Ref Target - Figure 3-8 UG918_c3_10_021815 Figure 3-8: TRD Setup Screen with a PCIe Device Detected PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 23 2. Open Device Manager (click Start > devmgmt.msc then press Enter) and look for the Xilinx PCI Express Device as shown in Figure 3-9. X-Ref Target - Figure 3-9 UG918_c3_11_040715 Figure 3-9: Xilinx PCI Express Device in Device Manager PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 24 Bringing Up the Design 3. Open a command prompt with administrator privileges, as shown in Figure 3-10. X-Ref Target - Figure 3-10 UG918_c3_12_040715 Figure 3-10: Command Prompt with Administrator Privileges PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 25 This step takes you to the Control and Monitoring GUI as shown in Figure 3-12, page X-Ref Target - Figure 3-11 UG918_c3-13_040715 Figure 3-11: GUI - TRD Setup Screen PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 26: Test The Reference Design

    GUI to the TRD Setup screen. Close the TRD Setup screen and power off the host machine and then the KCU105 board. On a Windows host computer, this step returns to the TRD Setup screen.
  • Page 27 Bringing Up the Design Remove Drivers from the Host Computer (Windows Only) Shutdown the host computer and power off the KCU105 board. Then use the following IMPORTANT: steps to remove the Windows drivers. 1. Power on the host computer and from Windows Explorer, navigate to the folder in which the reference design is downloaded (<dir>\kcu105_control_plane\software\windows\).

  • Page 28: Implementing The Base Design

    4. To run the implementation flow, enter: $ vivado -source trd01_base.tcl This opens the Vivado Integrated Design Environment (IDE), loads the block diagram, and adds the required top file and Xilinx design constraints (XDC) file to the project (see Figure 4-1).
  • Page 29 Chapter 4: Implementing and Simulating the Design X-Ref Target - Figure 4-1 UG918_c4_01_070717 Figure 4-1: Base Design—Project View PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 30 No Implementation Results are available is displayed. The generated bitstream can be found under the following directory: kcu105_control_plane/hardware/vivado/runs_base/trd01.runs/impl_1. X-Ref Target - Figure 4-2 UG918_c4_02_070717 Figure 4-2: Base Design—Generate Bitstream PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 31: Implementing The User Extension Design

    This opens the Vivado IDE, loads the block diagram, and adds the required top file and XDC file to the project (see Figure 4-3). X-Ref Target - Figure 4-3 UG918_c4_03_070717 Figure 4-3: User Extension Design—Project View PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 32: Simulating The Base Design Using Vivado Simulator

    The test bench initializes the bridge, does one double word (DW) write to BAR-mapped address space, reads back from the same address, and compares the data with expected pattern. PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 33 This opens the Vivado IDE with the target simulator set to the Vivado Simulator (Figure 4-5). X-Ref Target - Figure 4-5 UG918_c4_05_070717 Figure 4-5: Base Design Project Settings for Simulation PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 34 The result is shown in Figure 4-6. X-Ref Target - Figure 4-6 UG918_c4_06_070717 Figure 4-6: Base Design Behavioral Simulation using the Vivado Simulator PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 35: Hardware

    Figure 5-1 identifies the different TRD hardware design components. Subsequent sections discuss each of the components in detail. X-Ref Target - Figure 5-1 KCU105 Evaluation Board XCKU040-2FFVA1156E FPGA UG918_c5_01_021315 Figure 5-1: TRD Functional Block Diagram PCI Express Control Plane TRD www.xilinx.com...
  • Page 36 Table 5-1: Address Translation Maps Ingress Source Base Ingress Destination Base Comments BAR2 PCIe BAR2 mapped to power monitor slave 0x44A00000 BAR4 PCIe (BAR4) mapped to AXI block RAM 0xC0000000 PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 37 Converting AXI3 transactions from AXI-PCIe bridge into AXI4 transactions for various slaves • Decoding address to target appropriate slave See LogiCORE IP AXI Interconnect Product Guide (PG059) [Ref 7] for more details. PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 38 The block provides analog-to-digital conversion and monitoring capabilities. It enables reading of voltage and current on different power supply rails (supported on the KCU105 board) which are then used to calculate power. A lightweight PicoBlaze™ controller is used to set up the SYSMON registers in continuous sequence mode and read various rail data periodically.

  • Page 39: Data Flow

    1. The GUI issues a READ system call to read BAR-mapped registers based on your input. 2. The Character driver reads appropriate BAR-mapped registers and conveys the readings to the GUI. 3. The GUI displays the read BAR-mapped register information. PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 40: Software

    In Linux, the GUI installs the selected design mode drivers and can configure and ° control device and test parameters. In Windows, the GUI can configure and control device and test parameters. ° PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...

  • Page 41: Reference Design Modifications

    XIo_Out32((bar0_addr +REG_BRDG_BASE + REG_INGR_AXI_BASE + SECOND_TRANS +OFFSET_INGR_AXI_DST_LO ), 0xD0000000); This maps the newly added block RAM controller to BAR4. With this minor change, the same GUI can be used for read/write access. PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 42 The display from the software driver can be seen in the system dmesg log. The ability to read multiple user registers or block RAM controllers is not supported by the GUI, and the aperture size is currently limited to 4K. PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 43 Table A-1. For a detailed description of each folder, see the Readme file. X-Ref Target - Figure A-1 kcu105_control_plane Figure A-1: TRD Directory Structure PCI Express Control Plane TRD www.xilinx.com Send Feedback UG918 (v2017.2) July 18, 2017...
  • Page 44 Contains scripts to create a Vivado Design Suite project and outputs of Vivado runs ready to test Contains the BIT file to program the KCU105 PCI Express® Control Plane application software Contains software design deliverables for Linux and Windows...

  • Page 45: Recommended Practices

    1. If the GUI does not detect the board, open Device Manager and see if the drivers are loaded under Xilinx PCI Express Device. 2. If the drivers are not loaded, check the PCIe Link Up LED on the board (see Figure 3-6).

  • Page 46: Xilinx Resources

    1. Northwest Logic Expresso DMA Bridge Core 2. Vivado Design Suite User Guide Release Notes, Installation, and Licensing (UG973) 3. Kintex UltraScale FPGA KCU105 Evaluation Board User Guide (UG917) 4. LogiCORE IP UltraScale FPGAs Gen3 Integrated Block for PCI Express Product Guide...

  • Page 47: Please Read: Important Legal Notices

    Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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