Xilinx KCU105 User Manual page 56

Frequently Used Terms
Table 5-6 defines terms used in this document.
Table 5-6: Frequently Used Terms
Term
XDMA driver
application driver
host/system
Endpoint (EP) card
SGL
Source SGL
Destination SGL
S2C
C2S
Design Goals
Design goals for this TRD include the following:
• Provide a driver to facilitate I/Os over PCIe using Expresso DMA
• Present to the application driver a set of APIs using application drivers that can
perform high speed I/Os between the host (server) and EP
• Abstract the inner working of Expresso DMA which can be treated as a black box by
application drivers through APIs
• Create a common driver for different scenarios where the source and destination SGL
can reside on the host, EP, or both host and EP. In this TRD, the scenario of the host
software controlling source/destination SGL while EP hardware logic controlling
corresponding destination/source SGL is explored.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Low level driver to control the Expresso DMA. The driver is agnostic of the
applications stacked on top of it and serves the basic purpose of ferrying data
across the PCIe link.
Device driver layer stacked on the XDMA driver and hooks up with a protocol stack
or user space application. For example, Ethernet driver, user traffic generator.
Typically a server/desktop PC with PCIe connectivity.
PCIe Endpoint, an Ethernet card attached to PCIe slots of a server/desktop PC.
Scatter gather list. This is a software array with elements in the format proscribed
for Expresso DMA. This list is used to point to I/O buffers from/to which Expresso
DMA transfers data across a PCIe link. This SGL exists in the host system memory.
SGL used to point to source I/O buffers. Expresso DMA takes data from Source SGL
I/O buffers and drains into EP I/O buffers pointed to by buffer descriptors that are
populated by hardware logic in EP.
SGL used to point to destination I/O buffers. Expresso DMA takes data from EP I/O
buffers pointed to by buffer descriptors that are populated by hardware logic in EP
and drains into host I/O buffers pointed to by Destination SGL I/O buffers. The
Destination SGL is resident in the host system memory.
System to (PCIe) card. Data transfers from host I/O buffers (source) to EP I/O
buffers (destination).
(PCIe) card to system. Data transfer from EP I/O buffers (source) to host I/O buffers
(destination).
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