Resource Utilization - Xilinx KCU105 User Manual

Resource Utilization

Table 1-1 and Table 1-2
after synthesis. Place and route can alter these numbers based on placements and routing
paths. These numbers are to be used as a rough estimate of resource utilization. These
numbers might vary based on the version of the TRD and the tools used to regenerate the
design.
Table 1-1: Base Design Resource Utilization
Resource Type
CLB registers
CLB LUT
Block RAM
MMCME3_ADV
Global Clock Buffers
BUFG_GT
IOB
SYSMONE1
PCIE_3_1
GTHE3_CHANNEL
Table 1-2: User Extension Design Resource Utilization
Resource Type
CLB registers
CLB LUT
Block RAM
MMCME3_ADV
Global Clock Buffers
BUFG_GT
IOB
SYSMONE1
PCIE_3_1
GTHE3_CHANNEL
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
list the resources used by the TRD base and user extension designs
Available
484,800
242,400
600
10
240
120
520
1
3
20
Available
484,800
242,400
600
10
240
120
520
1
3
20
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Chapter 1: Introduction
Used Usage (%)
79,865
51,404
39.5
1
3
5
18
1
1
8
Used Usage (%)
101,313
64,884
80
1
3
12
23
1
1
10
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16.63
21.21
6.58
10
1.25
4.17
3.46
100
33.33
40
20.90
26.77
13.33
10
1.25
10.00
4.42
100
33.33
50
8