Xilinx KCU105 User Manual page 59

• EP memory: This memory is used to store I/O buffers from/to which Expresso DMA
transfers data to/from the host I/O buffers.
• Buffer descriptor (BD) FIFO: In the hardware SGL model, there is no SGL in EP. Instead,
there is a FIFO in which buffer descriptors pointing to I/O buffers in EP memory are
populated. Expresso DMA processes each BD and transfers data between the I/O buffer
pointed to by the BD and the host I/O buffer.
• Expresso DMA-aware hardware logic: This hardware logic is aware of the BD format
of Expresso DMA and its principles of operation. Whenever data is to be transferred
to/from host I/O buffers, this logic populates an appropriate BD in BD FIFO. Expresso
DMA then performs the I/O, resulting in data transfer.
• I/O buffer/FIFO: These are the memory locations on the host/EP from/to which
Expresso DMA actually performs data transfers. Expresso DMA makes use of buffer
descriptor elements and the loc_axi flag in these elements to determine the location of
source and destination of I/O buffers/FIFOs for data transfer. The XDMA driver on the
host and hardware logic on the EP mark the appropriate flag in the buffer descriptor to
facilitate data transfer.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
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