Simulating The Designs Using Vivado Simulator - Xilinx KCU105 User Manual

Simulating the Designs Using Vivado Simulator

Both the base and user extension TRD designs can be simulated using the Vivado simulator.
The testbench and the endpoint PCIe IP block are configured to use PHY Interface for PCI
Express (PIPE) mode simulation.
The test bench initializes the bridge and DMA, and sets up the DMA for system to card (S2C)
and card to system (C2S) data transfer. For the base design, the test bench configures the
DMA and hardware Generator/Checker to transfer one 64-byte packet in both the S2C and
C2S directions. For the Ethernet design, the datapaths are looped back at the PHY serial
interface. The test bench configures the DMA to transfer and receive one 64-byte packet in
the S2C and C2S direction, respectively.
Running Simulation using the Vivado Simulator
1. Open a terminal window on a Linux system and set up the Vivado environment or open
a Vivado Tcl shell on a Windows system.
2. Navigate to the kcu105_axis_dataplane/hardware/vivado/scripts folder.
3. To simulate the base design enter:
$ vivado -source trd03_base_xsim.tcl
This opens the Vivado IDE, loads the block diagram, and adds the required top file.
4. In the Flow Navigator, under Simulation, click Run Simulation and select Run
Behavioral Simulation (see
the Vivado simulator, and runs the simulation. The result is shown in
X-Ref Target - Figure 4-5
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 4: Implementing and Simulating the Design
Figure 4-5). This generates all the simulation files, loads
Figure 4-5: Run Behavioral Simulation
www.xilinx.com
Figure
UG920_c4_05_041117
Send Feedback
4-6.
38