Xilinx KCU105 User Manual page 57

SGL Model
In the SGL model of operation used in this TRD, all four SGLs corresponding to the four
DMA channels (one SGL per channel) reside in host memory. Note that a real-world use
case might not require all four channels to be operational.
For every channel, one source/destination SGL is used to point to I/O buffers in the host
memory. Corresponding source/destination scatter gather (SG) elements of the channel are
managed by hardware logic.
Based on application logic requirements, each channel (and a SGL corresponding to the
channel) is configured as IN/OUT. For example, an Ethernet application might configure
channel 0 to send Ethernet packets from the host to the EP (say the EP is an Ethernet host
bus adaptor (HBA) card for transmitting to the external world (S2C direction), while channel
1 is configured to get incoming Ethernet packets from the external world and send them
into host memory (C2S direction).
With this SGL model of operation, the application driver need not be aware of the memory
map of the PCIe EP because the driver does not have any control of the EP
source/destination location from which data is transferred. This model is typically used
where there is hardware logic in the EP that is aware of the Expresso DMA SGL format and
operating principles.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
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