Xilinx KCU105 User Manual page 6

The downstream AXI4-Lite slaves include a power monitor module, user space registers,
and an AXI performance monitor.
In the system to card direction (S2C), the DMA block moves data from host memory to the
FPGA through the integrated Endpoint block and then makes the data available at the AXI
streaming interface. In the card to system (C2S) direction, theDMA block uses the data
available on the AXI streaming interface and writes to host system memory through the
integrated Endpoint block.
The base design uses a simple generator/checker (GEN/CHK) block as a data
provider/consumer on the AXI streaming interface. This base platform can be extended to
a variety of applications such as Ethernet, and Crypto Engine.
The user extension design (shown in
network interface card. The Ethernet frames received from the host system are directed to
respective Ethernet ports for transmission, and incoming frames from Ethernet are directed
to the host after performing an address filtering operation.
X-Ref Target - Figure 1-2
User Root
App Complex
Depending on the user application, the two modules (red colored arrows) need to be changed.
All other blocks in the hardware design and software components can be reused.
Figure 1-2: KCU105 PCI Express Streaming Data Plane User Extension Design
The designs delivered as part of this TRD use Vivado® IP integrator to build the system. IP
Integrator provides intelligent IP integration in a graphical, Tcl-based,
correct-by-construction IP and system-centric design development flow. For further details
on IPI, see Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995)
[Ref 2].
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Figure 1-2) provides an example of a dual 10GbE
128 bits at
250 MHz
www.xilinx.com
Chapter 1: Introduction
Stream - 64 bits
MM - 128 bits
at 156.25 MHz
at 250 MHz
User Extension logic
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